PDF AD9071 Data sheet ( Hoja de datos )

Número de pieza	AD9071
Descripción	10-Bit 100 MSPS A/D Converter
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES 10-Bit, 100 MSPS ADC Low Power: 450 mW at 100 MSPS On-Chip Track/Hold 280 MHz Analog Bandwidth SINAD = 54 dB @ 41 MHz On-Chip Reference 1 V p-p Analog Input Range Single 5 V Supply Operation 5 V/3.3 V Outputs APPLICATIONS Digital Communications Signal Intelligence Digital Oscilloscopes Spectrum Analyzers Medical Imaging Sonar HDTV 10-Bit, 100 MSPS A/D Converter AD9071 FUNCTIONAL BLOCK DIAGRAM AD9071 AIN T/H AIN SUM AMP ENCODE TIMING VREF IN VREF OUT VCC – 2.5V ADC DAC ADC 10 ENCODE LOGIC VDD D0–D9 OR VCC GND GENERAL DESCRIPTION The AD9071 is a monolithic sampling analog-to-digital con- verter with an on-chip track-and-hold circuit and TTL/CMOS digital interfaces. The product operates at a 100 MSPS conver- sion rate with outstanding dynamic performance over its full operating range. The ADC requires only a single 5 V supply and an encode clock for full performance operation. The digital outputs are TTL compatible. Separate output power supply pins support interfacing with 3.3 V or 5 V logic. An out-of-range output (OR) is available that indicates a conversion result is outside the operating range. The output data are held at saturation levels during an out-of-range condition. The input amplifier supports differential or single-ended inter- faces. An internal reference is included. Fabricated on an advanced BiCMOS process, the AD9071 is available in a plastic SOIC package specified over the industrial temperature range (–40°C to +85°C). REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 1 page AD9071 SAMPLE N–1 SAMPLE N AIN ENCODE tA tEH SAMPLE N+1 tEL 1/fs SAMPLE N+3 SAMPLE N+2 SAMPLE N+4 D9–D0 DATA N–4 DATA N–3 DATA N–2 tPD DATA N–1 DATA N Figure 1. Timing Diagram tV DATA N+1 VCC AIN AIN VDD D9–0, OR Figure 2. Equivalent Analog Input Circuit VCC VREF IN Figure 5. Equivalent Digital Output Circuit VCC VREF OUT Figure 3. Equivalent Reference Input Circuit ENCODE VCC Figure 4. Equivalent Encode Input Circuit Figure 6. Equivalent Reference Output Circuit REV. C –5– 5 Page E3 1 VREF INT VREF EXT E1 E2 1 1 VREF SMB A IN J2 2, 3, 4, 5 - GND SMB A IN DIF J3 2, 3, 4, 5 - GND R4 50⍀ C7 0.1␮F R5 50⍀ C5 0.1␮F S3 T1 43 2 S9 S8 S5 R1 100⍀ S 10 GND 61 T1 – 1T S4 S6 ANALOG IN R19 100⍀ ANALOG IN C4 0.1␮F S7 C22 0.1␮F R32 25⍀ VCC C13 0.1␮F TP3 3 VREF OUT 4 D0 28 VREF IN D1 27 5 DNC 6 DNC U3 D2 26 25 D3 D4 24 AD9071 D5 19 9 AIN D6 18 D7 17 10 AIN 16 D8 15 D9 13 ENCODE 14 OR SMB J1 2, 3, 4, 5 - GND ENCODE IN R6 50⍀ S1 U5 74LCX86 13 2 ENCODE TP1 VCC : 2, 8, 11 VDD : 20, 22 GND : 1, 7 12, 21, 23 12 11 DATA CLK 13 R9 200⍀ R10 200⍀ R11 200⍀ R12 200⍀ R13 200⍀ R14 200⍀ R15 200⍀ R16 200⍀ R17 200⍀ R18 200⍀ TP2 R3 200⍀ U1 74LCX574 1 OUT EN 2 D0 3 D1 4 D2 5 D3 Q0 19 Q1 18 Q2 17 Q3 16 6 D4 7 D5 8 D6 9 D7 Q4 15 Q5 14 13 Q6 12 Q7 11 CLOCK GND : 10 +VD : 20 U2 74LCX574 1 OUT EN 2 19 D0 Q0 3 18 D1 Q1 4 17 D2 Q2 5 16 D3 Q3 6 15 D4 Q4 7 14 D5 Q5 8 13 D6 Q6 9 12 D7 Q7 11 CLOCK DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 OR DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 OR R27 100⍀ DATABIT 0 R26 100⍀ DATABIT 1 R25 100⍀ DATABIT 2 R24 100⍀ DATABIT 3 R23 100⍀ DATABIT 4 R22 100⍀ DATABIT 5 R21 100⍀ DATABIT 6 R20 100⍀ DATABIT 7 R29 100⍀ DATABIT 8 R28 100⍀ DATABIT 9 R30 100⍀ OVERRANGE R33 GND : 10 0⍀ S2 9 10 8 DATA READY TP5 +VD : 20 DATA READY R36 150⍀ R 31 4.99k⍀ +VD 4 6 5 + VD : 14 GND : 7 TP4 +VD R34 150⍀ DB0 DB1 DB2 R35 150⍀ +VD J5 1 2 3 TB1 1 2 3 4 5 6 TB6 GND VCC C1 0.1␮F VDD +VD VREF EXT C20 10␮F C17 0.1␮F C21 10␮F C6 0.1␮F C11 0.1␮F VCC C18 10␮F VDD C12 0.1␮F 10 9 8 7 6 5 4 3 2 1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 28 CLK AD9760 DB3 DB4 DB5 DB6 DB7 DB8 DB9 22 IOUTA DAC OUT SNS J4 2, 3, 4, 5, - GND 4 5 6 7 8 9 10 11 12 13 14 C19 10␮F C17 0.1␮F C8 0.1␮F C15 0.1␮F C3 0.1␮F +VD C2 0.1␮F IOUTB DVDD AVDD COMP2 COMP1 FSADJ REFIO REFLO SLEEP 21 27 24 23 19 18 17 16 15 S13 R7 50⍀ 15 16 17 +VD C14 0.1␮F C9 0.1␮F R2 2k⍀ C10 0.1␮F S11 S12 +VD R8 50⍀ 18 19 20 GND GND R37 150⍀ GND C37DPPF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 P2 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 DATA READY DATABIT 0 DATABIT 1 DATABIT 2 DATABIT 3 DATABIT 4 DATABIT 5 DATABIT 6 DATABIT 7 DATABIT 8 DATABIT 9 OVERRANGE 11 Page

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