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AD9054A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9054A
Beschreibung 8-Bit / 200 MSPS A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD9054A Datasheet, Funktion
a
FEATURES
200 MSPS Guaranteed Conversion Rate
135 MSPS Low Cost Version Available
350 MHz Analog Bandwidth
1 V p-p Analog Input Range
Internal 2.5 V Reference and T/H
Low Power: 500 mW
5 V Single Supply Operation
TTL Output Interface
Single or Demultiplexed Output Ports
APPLICATIONS
RGB Graphics Processing
High Resolution Video
Digital Data Storage Read Channels
Digital Communications
Digital Instrumentation
Medical Imaging
8-Bit, 200 MSPS
A/D Converter
AD9054A
AIN
AIN
ENCODE
ENCODE
FUNCTIONAL BLOCK DIAGRAM
VREF IN
VREF OUT
AD9054A
2.5V REFERENCE
T/H
TIMING
QUANTIZER
8
ENCODE
LOGIC
DEMULTIPLEXER 8
DA7 – D A0
DB7 – D B0
VDD GND
DEMUX
DS DS
GENERAL DESCRIPTION
The AD9054A is an 8-bit monolithic analog-to-digital converter
optimized for high speed, low power, small size and ease of use.
With a 200 MSPS encode rate capability and full-power analog
bandwidth of 350 MHz, the component is ideal for applications
requiring the highest possible dynamic performance.
To minimize system cost and power dissipation, the AD9054A
includes an internal 2.5 V reference and track-and-hold circuit.
The user provides only a 5 V power supply and an encode clock.
No external reference or driver components are required for
many applications.
The AD9054A’s encode input interfaces directly to TTL, CMOS
or positive-ECL logic and will operate with single-ended or
differential inputs. The user may select dual-channel or single-
channel digital outputs. The dual (demultiplexed) mode inter-
leaves ADC data through two 8-bit channels at one-half the
clock rate. Operation in demultiplexed mode reduces the speed
and cost of external digital interfaces while allowing the ADC to
be clocked to the full 200 MSPS conversion rate. In the single-
channel (nondemultiplexed) mode, all data is piped at the full
clock rate to the Channel A outputs.
Fabricated with an advanced BiCMOS process, the AD9054A is
provided in a space-saving 44-lead LQFP surface mount plastic
package (ST-44) and specified over the full industrial (–40°C to
+85°C) temperature range.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001






AD9054A Datasheet, Funktion
AD9054A
SAMPLE N1
SAMPLE N
AIN
SAMPLE N+3 SAMPLE N+4
SAMPLE N+5
SAMPLE N2
ENCODE
tA
tEH tEL
1/fS
ENCODE
DS
tHDS
tSDS
tHDS
tSDS
DS
PORT A
D7 D 0
DATA N7
OR N8
tPWDS
DATA N7
OR N6
SAMPLE N+1
SAMPLE N+2
tPD
INVALID IF OUT OF SYNC
DATA N4 IF IN SYNC
tV
DATA N2
SAMPLE N+6
DATA N
PORT B
D7 D 0
DATA N8
OR N7
DATA N6
OR N7
INVALID IF OUT OF SYNC
DATA N5 IF IN SYNC
DATA N3
Figure 2a. Timing—Dual Channel Mode (One-Shot Data Sync)
DATA N1
DATA N+1
SAMPLE N1
SAMPLE N
AIN
SAMPLE N+3 SAMPLE N+4
SAMPLE N+5
SAMPLE N2
ENCODE
ENCODE
DS
DS
tHDS
tA
tEH tEL
1/fS
tSDS tHDS
tSDS
tPWDS
PORT A
D7 D 0
DATA N7
OR N8
DATA N7
OR N6
SAMPLE N+1 SAMPLE N+2
tPD
INVALID IF OUT OF SYNC
DATA N4 IF IN SYNC
tV
DATA N2
SAMPLE N+6
DATA N
PORT B
D7 D 0
DATA N8
OR N7
DATA N6
OR N7
INVALID IF OUT OF SYNC
DATA N5 IF IN SYNC
DATA N3
DATA N1
Figure 2b. Timing—Dual Channel Mode (Continuous Data Sync)
DATA N+1
–6– REV. D

6 Page









AD9054A pdf, datenblatt
AD9054A
2.502
2.501
2.500
2.499
2.498
40 20 0 20 40 60 80 100
TAMB ؇C
TPC 25. Reference Voltage vs. Temperature
APPLICATION NOTES
THEORY OF OPERATION
The AD9054A combines Analog Devices’ patented MagAmp
bit-per-stage architecture with flash converter technology to
create a high performance, low power ADC. For ease of use the
part includes an on-board reference and input logic that accepts
TTL, CMOS or PECL levels.
The analog input signal is buffered by a high-speed differential
amplifier and applied to a track-and-hold (T/H) circuit. This T/H
captures the value of the input at the sampling instant and
maintains it for the duration of the conversion. The sampling
and conversion process is initiated by a rising edge on the
ENCODE input. Once the signal is captured by the T/H, the
four Most Significant Bits (MSBs) are sequentially encoded by
the MagAmp string. The residue signal is then encoded by a
flash comparator string to generate the four Least Significant
Bits (LSBs). The comparator outputs are decoded and com-
bined into the 8-bit result.
If the user has selected Single Channel Mode (DEMUX =
HIGH), the 8-bit data word is directed to the Channel A out-
put bank. Data are strobed to the output on the rising edge of
the ENCODE input with four pipeline delays. If the user has
selected Dual Channel Mode (DEMUX = LOW) the data are
alternately directed between the A and B output banks and have
five pipeline delays. At power-up, the N sample data can appear
at either the A or B port. To align the data in a known state the
user must strobe DATA SYNC (DS, DS) per the conditions
described in the Timing section.
Graphics Applications
The high bandwidth and low power of the AD9054A make it very
attractive for applications that require the digitization of presampled
waveforms, wherein the input signal rapidly slews from one
level to another and is relatively stable for a period of time.
Examples of these include digitizing the output of computer
graphic display systems and very high speed solid state imagers.
These applications require the converter to process inputs with
frequency components well in excess of the sampling rate (often
with subnanosecond rise times), after which the A/D must settle
and sample the input in well under one pixel time. The architec-
ture of the AD9054A is vastly superior to older flash architectures,
that not only exhibit excessive input capacitance (which is very
hard to drive), but can make major errors when fed a very rap-
idly slewing signal. The AD9054A’s extremely wide bandwidth
Track/Hold circuit processes these signals without difficulty.
Using the AD9054A
Good high speed design practices must be followed when using
the AD9054A. To obtain maximum benefit, decoupling capaci-
tors should be physically as close to the chip as possible. We
recommend placing a 0.1 µF capacitor at each power-ground
pin pair (9 total) for high frequency decoupling, and including
one 10 µF capacitor for local low frequency decoupling. The
VREF IN pin should also be decoupled by a 0.1 µF capacitor.
The part should be located on a solid ground plane and output
trace lengths should be short (<1 inch) to minimize transmis-
sion line effects. This avoids the need for termination resistors
on the output bus and reduces the load capacitance that needs
to be driven, which in turn minimizes on-chip noise due to
heavy current flow in the outputs. We have obtained optimum
performance on our evaluation board by tying all VDD pins to a
quiet analog power supply system, and tying all GND pins to a
quiet analog system ground.
Minimum Encode Rate
The minimum sampling rate for the AD9054A is 25 MHz.
To achieve very high sampling rates, the track/hold circuit
employs a very small hold capacitor. When operated below the
minimum guaranteed sampling rate, the T/H droop becomes
excessive. This is first observed as an increase in offset voltage,
followed by degraded linearity at even lower frequencies.
Lower effective sampling rates may be easily supported by oper-
ating the converter in dual port output mode and using only
one output channel. A majority of the power dissipated by the
AD9054A is static (not related to conversion rate) so the penalty
for clocking at twice the desired rate is not high.
Reference
The AD9054A internal reference, VREF, provides a simple, cost
effective reference for many applications. It exhibits reasonable
accuracy and excellent stability over power supply and tempera-
ture variations. The VREF OUT pin can simply be strapped to
the VREF IN pin. The internal reference can be used to drive
additional loads (up to several mA), including multiple A/D con-
verters as might be required in a triple video converter application.
When an external reference is desired for accuracy or other
requirements, the AD9054A should be driven directly by the
external reference source connected to pin VREF IN (VREF
OUT can be left floating). The external reference can be set to
2.5 V ± 0.25 V. If VREF IN is raised by 10% (set to 2.75 V) the
analog full-scale range will increase by 10% to 1.024 × 1.1 =
1.1264 V. The new input range will then be AIN ± 0.5632 V.
–12–
REV. D

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