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AD9048 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9048
Beschreibung Monolithic 8-Bit Video A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 8 Seiten
AD9048 Datasheet, Funktion
a
Monolithic 8-Bit
Video A/D Converter
AD9048
FEATURES
35 MSPS Encode Rate
16 pF Input Capacitance
550 mW Power Dissipation
Industry-Standard Pinouts
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Professional Video Systems
Special Effects Generators
Electro-Optics
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
GENERAL DESCRIPTION
The AD9048 is an 8-bit, 35 MSPS flash converter, made on
a high speed bipolar process, which is an alternate source for
the TDC1048 unit, and offers enhancements over its
predecessor. Lower power dissipation makes the AD9048
attractive for a variety of system designs.
Because of its wide bandwidth, it is an ideal choice for real-time
conversion of video signals. Input bandwidth is flat with no
missing codes.
Clocked latching comparators, encoding logic, and output
buffer registers operating at minimum rates of 35 MSPS pre-
clude a need for a sample-and-hold (S/H) or track-and-hold
(T/H) in most system designs using the AD9048. All digital
control inputs and outputs are TTL compatible.
Devices operating over two ambient temperature ranges and
with two grades of linearity are available. Linearities of either
0.5 LSB or 0.75 LSB can be ordered for a commercial range of
0°C to 70°C or extended case temperatures of –55°C to +125°C.
FUNCTIONAL BLOCK DIAGRAM
NLINV 12
NMINV 28
VIN 23
RT 18
R
R
RM 27
R/2
R/2
1
2
127
128
R
254
R
RB 26
255
CONVERT 17
6 10
789
AD9048
1 D1 (MSB)
E
N 2 D2
C
O 3 D3
DL
I A 4 D3
NT
G C 13 D5
H
L 14 D6
O
G 15 D7
I
C 16 D8 (LSB)
5 11 19 25
VCC VEE DGND AGND
Commercial versions are packaged in 28-lead DIPs; extended
temperature versions are available in ceramic DIP and ceramic
LCC packages. Both commercial units and MIL-STD-883 units
are standard products.
The AD9048 A/D converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military Prod-
ucts Databook or current AD9048/883B data sheet for detailed
specifications.
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






AD9048 Datasheet, Funktion
AD9048
THEORY OF OPERATION
Refer to the Functional Block Diagram of the AD9048. The
AD9048 comprises three functional sections: a comparator
array, encoding logic, and output latches.
Within the array, the analog input signal to be digitized is
compared with 255 reference voltages. The outputs of all com-
parators whose references are below the input signal level will be
high; outputs whose references are above that level will be low.
The n-of-255 code that results from this comparison is applied
to the encoding logic where it is converted into binary coding.
When it is inverted with dc signals applied to the NLINV and/or
NMINV pins, it becomes twos complement.
After encoding, the signal is applied to the output latch circuits
where it is held constant between updates controlled by the
application of CONVERT pulses.
The AD9048 uses strobed latching comparators in which com-
parator outputs are either high or low, as dictated by the analog
input level. Data appearing at the output pins have a pipeline
delay of one encode cycle.
Input signal levels between the references applied to RT (Pin 18)
and RB (Pin 26) will appear at the output as binary numbers
between 0 and 255, inclusive. Signals outside that range will
show up as either full-scale positive or full-scale negative out-
puts. No damage will occur to the AD9048 as long as the input
is within the voltage range of VEE to 0.5 V.
The significantly reduced input capacitance of the AD9048
lowers the drive requirements of the input buffer/amplifier and
also induces much smaller phase shift in the analog input signal.
Applications that depend on controlled phase shift at the con-
verter input can benefit from using the AD9048 because of its
inherently lower phase shift.
The CONVERT, analog input, and digital output circuits are
shown in Figure 3.
5.0V
13k
5.0V
CONVERT
DIGITAL
OUTPUTS
System timing, which provides details on delays through the
AD9048 as well as the relationships of various timing events, is
shown in Figure 4.
ANALOG
INPUT
N
N+1
N+2
CONVERT
APERTURE
DELAY
OUTPUT
DATA
tOH
N–1
N N+1
tPD
DATA
DATA
CHANGING
CHANGING
Figure 4. Timing Diagram
Dynamic performance of the AD9048, i.e., typical signal-to-
noise ratio, is illustrated in Figures 5 and 6.
50
48
46
44
42
40
38
100kHz
1MHz
10MHz
ANALOG INPUT FREQUENCY – 1dB BELOW FULL-SCALE
Figure 5. Dynamic Performance (20 MHz Encode Rate)
50
48
46
RT
R
44
42
ANALOG
INPUT
–5.2V
–5.2V
R/2
RM
R/2
–5.2V
–5.2V
COMPARATOR CELLS
Figure 3. Input/Output Circuits
R
RB
40
38
100kHz
1MHz
10MHz
ANALOG INPUT FREQUENCY – 1dB BELOW FULL-SCALE
Figure 6. Dynamic Performance (35 MHz Encode Rate)
–6– REV. F

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