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PDF AD8151 Data sheet ( Hoja de datos )
| Número de pieza | AD8151 | |
| Descripción | Digital Crosspoint Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8151 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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FEATURES
Low cost
33 × 17, fully differential, nonblocking array
3.2 Gbps per port NRZ data rate
Wide power supply range: +3.3 V, –3.3 V
Low power
425 mA (outputs enabled)
35 mA (outputs disabled)
LV PECL- and LV ECL-compatible
CMOS/TTL-level control inputs: 3 V to 5 V
Low jitter
No heat sinks required
Drives a backplane directly
Programmable output current
Optimize termination impedance
User-controlled voltage at the load
Minimize power dissipation
Individual output disable for busing and reducing power
Double row latch
Buffered inputs
184-lead LQFP package
GENERAL DESCRIPTION
The AD81511 is a member of the Xstream line of products,
offering a breakthrough in digital switching and a large switch
array (33 × 17) on very little power—typically less than 1.5 W.
It also operates at data rates in excess of 3.2 Gbps per port,
making it suitable for Sonet OC-48 applications with
8/10-bit forward-error correction (FEC). Furthermore, the
price of the AD8151 makes it affordable enough to be used for
lower data rates. The AD8151’s flexible supply voltages allow
the user to operate with either emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL) data levels, and with 3.3
V for further power reduction. The control interface is CMOS-
/TTL-compatible (3 V to 5 V).
Its fully differential signal path reduces jitter and crosstalk,
while allowing the use of smaller, single-ended voltage swings.
The AD8151 is offered in a 184-lead LQFP package that
operates over the extended commercial temperature range
of 0°C to 85°C.
33 × 17, 3.2 Gbps
Digital Crosspoint Switch
AD8151
APPLICATIONS
High speed serial backplane routing to Sonet OC-48
applications with FEC
Fiber optic network switching
Fiber channel
LVDS
FUNCTIONAL BLOCK DIAGRAM
INP INN
CS
RE 33 33
7
D
A5
FIRST
RANK
17 ×
7-BIT
LATCH
SECOND
RANK
17 ×
7-BIT
LATCH
17
33 × 17
DIFFERENTIAL
SWITCH
MATRIX 17
OUTP
OUTN
WE
UPDATE
RESET
.
AD8151
Figure 1.
70ps/DIV
Figure 2. Eye Pattern, 3.2 Gbps, PRBS 23
1 Patent pending.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VEE
IN20P
IN20N
VEE
IN21P
IN21N
VEE
IN22P
IN22N
VEE
IN23P
IN23N
VEE
IN24P
IN24N
VEE
IN25P
IN25N
VEE
IN26P
IN26N
VEE
IN27P
IN27N
VEE
IN28P
IN28N
VEE
IN29P
IN29N
VEE
IN30P
IN30N
VEE
IN31P
IN31N
VEE
IN32P
IN32N
VEE
VCC
VEE
OUT16N
OUT16P
VEEA16
VEE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
PIN 1
INDICATOR
AD8151
184L LQFP
TOP VIEW
(Not to Scale)
Figure 4. Pin Configuration
Rev. B | Page 5 of 40
AD8151
138 VEE
137 IN12N
136 IN12P
135 VEE
134 IN11N
133 IN11P
132 VEE
131 IN10N
130 IN10P
129 VEE
128 IN09N
127 IN09P
126 VEE
125 IN08N
124 IN08P
123 VEE
122 IN07N
121 IN07P
120 VEE
119 IN06N
118 IN06P
117 VEE
116 IN05N
115 IN05P
114 VEE
113 IN04N
112 IN04P
111 VEE
110 IN03N
109 IN03P
108 VEE
107 IN02N
106 IN02P
105 VEE
104 IN01N
103 IN01P
102 VEE
101 IN00N
100 IN00P
99 VEE
98 VCC
97 VEEA0
96 OUT00P
95 OUT00N
94 VEEA1
93 VEE
5 Page 
p-p = 43ps
STD DEV = 8ps
p-p = 43ps
STD DEV = 8ps
AD8151
1.4ns/DIV
Figure 17. Response, 2.5 Gbps,
32-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011
100
90
80
70
60
50 2.5Gbps JITTER
40
30
3.2Gbps JITTER
20
10
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
INPUT AMPLITUDE (V)
Figure 18. Jitter vs. Single-Ended Input Amplitude, PRBS 23
100
90
80
70
60
3.2Gbps
50
2.5Gbps
40
30
20
10
0
–1.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2
VIH (V)
0
0.2 0.4 0.6
Figure 19. Jitter vs. VIH, PRBS 23
1.1ns/DIV
Figure 20. Response, 3.2 Gbps,
32-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011
100
90
80
3.2Gbps
70
60
50
2.5Gbps
40
30
20
10
0
–5.0 –4.8 –4.6 –4.4 –4.2 –4.0 –3.8 –3.6 –3.4 –3.2 –3.0
VEE (V)
Figure 21. Jitter vs. Supply, PRBS 23
100
90
80
70
3.2Gbps
60
50
2.5Gbps
40
30
20
10
0
–1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2
VOH (V)
0
0.2
Figure 22. Jitter vs. VOH, PRBS 23, Output Amplitude = 0.4 V Single-Ended
Rev. B | Page 11 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD8151.PDF ] | |
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