PDF AD808 Data sheet ( Hoja de datos )

Número de pieza	AD808
Descripción	Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
Fabricantes	Analog Devices
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No Preview Available ! a Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD808 FEATURES Meets CCITT G.958 Requirements for STM-4 Regenerator—Type A Meets Bellcore TR-NWT-000253 Requirements for OC-12 Output Jitter: 2.5 Degrees RMS 622 Mbps Clock Recovery and Data Retiming Accepts NRZ Data, No Preamble Required Phase-Locked Loop Type Clock Recovery— No Crystal Required Quantizer Sensitivity: 4 mV Level Detect Range: 10 mV to 40 mV, Programmable Single Supply Operation: +5 V or –5.2 V Low Power: 400 mW 10 KH ECL/PECL Compatible Output Package: 16-Lead Narrow 150 mil SOIC PRODUCT DESCRIPTION The AD808 provides the receiver functions of data quantiza- tion, signal level detect, clock recovery and data retiming for 622 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly inte- grated, low cost, low power SONET OC-12 or SDH STM-4 fiber optic receiver. The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable thresh- old. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output. The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee frequency acquisition without false lock. This eliminates a reli- ance on external components such as a crystal or a SAW filter, to aid frequency acquisition. The AD808 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pat- tern jitter throughout the AD808. The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.5 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance. The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer require- ments can easily be met with a damping factor of 5 or greater. Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency. The AD808 consumes 400 mW and operates from a single power supply at either +5 V or –5.2 V. FUNCTIONAL BLOCK DIAGRAM QUANTIZER PIN NIN THRADJ SIGNAL LEVEL DETECTOR LEVEL DETECT COMPARATOR/ BUFFER CF1 CF2 ⌽DET COMPENSATING ZERO PHASE-LOCKED LOOP ⌺ FDET AD808 RETIMING DEVICE LOOP FILTER VCO CLKOUTP CLKOUTN DATAOUTP DATAOUTN SDOUT REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 1 page AD808 Damping Factor, ζ Damping factor, ζ describes the compensation of the second order PLL. A larger value of ζ corresponds to more damping and less peaking in the jitter transfer function. Acquisition Time This is the transient time, measured in bit periods, required for the AD808 to lock onto input data from its free-running state. Symmetry—Recovered Clock Duty Cycle Symmetry is calculated as (100 × on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its “0” level and its “1” level. INPUT VCM 4mVp-p SCOPE PROBE AD808 QUANTIZER BINARY OUTPUT VCM a. Single-Ended Input Application VCM 2mVp-p +INPUT –INPUT SCOPE PROBE AD808 QUANTIZER BINARY OUTPUT VCM b. Differential Input Application Figure 3. (a–b) Single-Ended and Differential Input Applications The AD808 has internal circuits to set the common-mode volt- age at the quantizer inputs PIN (Pin 13) and NIN (Pin 12) as shown in Figure 4a. This allows very simple capacitive coupling of the signal from the preamp in the AD808 as shown in Figure 3. The internal common-mode potential is a diode drop (ap- proximately 0.8 V) below the positive supply as shown in Figure 4a. Since the common mode is referred to the positive supply, it is useful to bypass the common mode of the preamp to the positive supply as well, if this is an option. Note, it is not neces- sary to use capacitive coupling of the input signal with the AD808. Figure 14 shows the input common-mode voltage can be externally set. PIN 5k⍀ 5k⍀ NIN AVCC 500⍀ 500⍀ OUT AVEE a. Quantizer Differential Input Stage 1.2V +VBE 6k⍀ THRADJ 80k⍀ AVEE b. Threshold Adjust VCC1 IOH 30⍀ SDOUT 30⍀ IOL VEE c. Signal Detect Output (SDOUT) 140⍀ 140⍀ VCC2 DIFFERENTIAL OUTPUT 7.8mA VEE d. PLL Differential Output Stage—DATAOUT(N), CLKOUT(N) Figure 4. (a–d) Simplified Schematics REV. 0 –5– 5 Page –11– 11 Page

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