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PDF ADM1181A Data sheet ( Hoja de datos )
| Número de pieza | ADM1181A | |
| Descripción | RS-232 Line Drivers/Receivers | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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EMI/EMC-Compliant, ±15 kV, ESD-Protected
RS-232 Line Drivers/Receivers
ADM202E/ADM1181A
FEATURES
Complies with 89/336/EEC EMC directive
ESD protection to IEC1000-4-2 (801.2)
±8 kV: contact discharge
±15 kV: air-gap discharge
±15 kV: human body model
EFT fast transient/burst immunity (IEC1000-4-4)
Low EMI emissions (EN55022)
230 kbits/s data rate guaranteed
TSSOP package option
Upgrade for MAX202E, 232E, LT1181A
APPLICATIONS
General-purpose RS-232 data link
Portable instruments
PDAs
GENERAL DESCRIPTION
The ADM202E and ADM1181A are robust, high speed,
2-channel RS-232/V.28 interface devices that operate from a
single 5 V power supply. Both products are suitable for operation
in harsh electrical environments and are compliant with the EU
directive on EMC (89/336/EEC). Both the level of electromagnetic
emissions and immunity are in compliance. EM immunity
includes ESD protection in excess of ±15 kV on all I/O lines,
fast transient/burst protection (1000-4-4), and radiated
immunity (1000-4-3). EM emissions include radiated and
conducted emissions as required by Information Technology
Equipment EN55022, CISPR22.
The ADM202E and ADM1181A conform to the EIA-232E
and CCITT V.28 specifications and operate at data rates up
to 230 kbps.
Four external 0.1 µF charge-pump capacitors are used for the
voltage doubler/inverter, permitting operation from a single
5 V supply.
FUNCTIONAL BLOCK DIAGRAMS
5V INPUT
0.1µF
10V
0.1µF
10V
C1+ +5V TO +10V VCC
VOLTAGE
C1– DOUBLER V+
C2+ +10V TO –10V V–
VOLTAGE
C2– INVERTER
C3
0.1µF
6.3V
C4
0.1µF
10V
C5
0.1µF
CMOS
INPUTS
T1IN
T2IN
T1
T2
T1OUT
T2OUT
EIA/TIA-232
OUTPUTS
CMOS
OUTPUTS
R1OUT
R2OUT
R1
R2
R1IN
R2IN
EIA/TIA-232
INPUTS*
GND ADM202E
*INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT
Figure 1.
5V INPUT
0.1µF
10V
0.1µF
10V
CMOS
INPUTS
T1IN
T2IN
C1+
+5V TO +10V
VOLTAGE
VCC
C1– DOUBLER V+
C2+ +10V TO –10V V–
VOLTAGE
C2– INVERTER
T1
T2
C5
0.1µF
C3
0.1µF
10V
C4 10V
0.1µF
10V
T1OUT
T2OUT
EIA/TIA-232
OUTPUTS
CMOS
OUTPUTS
R1OUT
R2OUT
R1
R2
GND ADM1181A
R1IN
R2IN
EIA/TIA-232
INPUTS*
*INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT
Figure 2.
The ADM202E provides a robust pin-compatible upgrade for
existing ADM202, ADM232L, or MAX202E/MAX232E sockets.
It is available in a 16-lead PDIP, a wide SOIC, a narrow SOIC,
and a space-saving TSSOP package that is 44% smaller than the
SOIC package.
The ADM1181A provides a robust pin-compatible upgrade for
the LTC1181A, and it is available in a 16-lead PDIP package
and a wide 16-lead SOIC package.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
C1+ 1
16 VCC
V+ 2
15 GND
C1– 3 ADM202E 14 T1OUT
ADM1181A
C2+ 4
13 R1IN
C2–
5
TOP VIEW 12
(Not to Scale)
R1OUT
V– 6
11 T1IN
T2OUT 7
10 T2IN
R2IN 8
9 R2OUT
Figure 3. Pin Configuration
ADM202E/ADM1181A
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
16 VCC
Power Supply Input: 5 V ± 10%.
2 V+ Internally Generated Positive Supply (+9 V nominal).
6 V− Internally Generated Negative Supply (−9 V nominal).
15
GND
Ground Pin. Must be connected to 0 V.
1, 3
C1+, C1−
External Capacitor 1 is connected between these pins. A 0.1 µF capacitor is recommended, but larger
capacitors of up to 47 µF can be used.
4, 5
C2+, C2−
External Capacitor 2 is connected between these pins. A 0.1 µF capacitor is recommended, but larger
capacitors of up to 47 µF can be used.
10, 11
TIN
Transmitter (Driver) Inputs. These inputs accept TTL/CMOS levels.
7, 14
TOUT
Transmitter (Driver) Outputs. These are RS-232 signal levels (typically ±9 V).
8, 13
RIN
Receiver Inputs. These inputs accept RS-232 signal levels. An internal 5 kΩ pull-down resistor to GND is
connected on each input.
9, 12
ROUT
Receiver Outputs. These are CMOS output logic levels.
0.1µF
10V
0.1µF
10V
CMOS
INPUTS
T1IN
T2IN
5V INPUT
1 C1+ +5V TO +10V VCC 16
VOLTAGE
3 C1– DOUBLER V+ 2
4 C2+ +10V TO –10V V– 6
VOLTAGE
5 C2– INVERTER
11 T1
14
10 T2
7
C3
0.1µF
6.3V
C4
0.1µF
10V
C5
0.1µF
T1OUT
T2OUT
EIA/TIA-232
OUTPUTS
CMOS
OUTPUTS
R1OUT
R2OUT
12
9
R1
R2
13 R1IN
EIA/TIA-232
INPUTS*
8 R2IN
GND ADM202E
15
*INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT
Figure 4. ADM202E Typical Operating Circuit
0.1µF
10V
0.1µF
10V
CMOS
INPUTS
T1IN
T2IN
5V INPUT
1 C1+
+5V TO +10V
VOLTAGE
VCC
16
3 C1– DOUBLER V+ 2
4 C2+ +10V TO –10V V– 6
VOLTAGE
5 C2– INVERTER
11 T1
14
10 T2
7
C5
0.1µF
C3 10V
0.1µF
C4 10V
0.1µF
10V
T1OUT
T2OUT
EIA/TIA-232
OUTPUTS
CMOS
OUTPUTS
R1OUT
R2OUT
12
9
R1 13 R1IN
R2 8
GND ADM1181A
15
R2IN
EIA/TIA-232
INPUTS*
*INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT
Figure 5. ADM1181A Typical Operating Circuit
Rev. C | Page 5 of 16
5 Page 
Table 4. IEC1000-4-2 Compliance Levels
Level
Contact Discharge Air Discharge
1 2 kV
2 kV
2 4 kV
4 kV
3 6 kV
8 kV
4 8 kV
15 kV
Table 5. ADM202E/ADM1181A ESD Test Results
ESD Test Method
I/O Pins
MIL-STD-883B
±15 kV
IEC1000-4-2
Contact
±8 kV
Air ±15 kV
FAST TRANSIENT/BURST TESTING (IEC1000-4-4)
IEC1000-4-4 (previously 801-4) covers electrical fast transient
(EFT)/burst immunity. Electrical fast transients occur as a result
of arcing contacts in switches and relays. The tests simulate the
interference generated when, for example, a power relay
disconnects an inductive load. A spark is generated due to the
well-known back EMF effect. In fact, the spark consists of a
burst of sparks as the relay contacts separate. The voltage
appearing on the line, therefore, consists of a burst of extremely
fast transient impulses. A similar effect occurs when switching
on fluorescent lights.
The fast transient/burst test defined in IEC1000-4-4 simulates
this arcing, and its waveform is illustrated in Figure 17. It
consists of a burst of 2.5 kHz to 5 kHz transients repeating at
300 ms intervals. It is specified for both power and data lines.
V
5ns
V
300ms
15ms
t
50ns
0.2/ 0.4ms
Figure 21. IEC1000-4-4 Fast Transient Waveform
t
ADM202E/ADM1181A
A simplified circuit diagram of the actual EFT generator is
illustrated in Figure 22.
The transients are coupled onto the signal lines using an EFT
coupling clamp. The clamp, which is 1 m long, completely
surrounds the cable, providing maximum coupling capacitance
(50 pF to 200 pF typ) between the clamp and the cable. High
energy transients are capacitively coupled to the signal lines.
Fast rise times (5 ns), as specified by the standard, result in very
effective coupling. This test is very strenuous because high voltages
are coupled onto the signal lines. The repetitive transients often
cause problems where single pulses do not. Destructive latch-up
can be induced due to the high energy content of the transients.
Note that this stress is applied while the interface products are
powered up and transmitting data. The EFT test applies
hundreds of pulses with higher energy than ESD. Worst-case
transient current on an I/O line can be as high as 40 A.
HIGH
VOLTAGE
SOURCE
RC
CC
L RM CD
ZS
50Ω
OUTPUT
Figure 22. IEC1000-4-4 Fast Transient Generator
Test results are classified according to the following:
• Classification 1: Normal performance within specifi-
cation limits
• Classification 2: Temporary degradation or loss of
performance that is self-recoverable
• Classification 3: Temporary degradation or loss of function
or performance that requires operator intervention or
system reset
• Classification 4: Degradation or loss of function that is not
recoverable due to damage
The ADM202E/ADM1181A meet Classification 2 and have
been tested under worst-case conditions using unshielded
cables. Data transmission during the transient condition is
corrupted, but can resume immediately following the EFT event
without user intervention.
Rev. C | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADM1181A.PDF ] | |
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