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ADM1021A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADM1021A
Beschreibung System Temperature Monitor Microcomputer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADM1021A Datasheet, Funktion
Low Cost Microprocessor,
System Temperature Monitor Microcomputer
ADM1021A
FEATURES
PRODUCT DESCRIPTION
Alternative to the ADM1021
On-chip and remote temperature sensing
No calibration necessary
1°C accuracy for on-chip sensor
3°C accuracy for remote sensor
Programmable overtemperature/undertemperature
limits
Programmable conversion rate
2-wire SMBus serial interface
Supports system management bus (SMBus) alert
200 μA max operating current
1 μA standby current
3 V to 5.5 V supply
Small 16-lead QSOP package
APPLICATIONS
Desktop computers
Notebook computers
Smart batteries
Industrial controllers
Telecom equipment
Instrumentation
The ADM1021A1 is a two-channel digital thermometer and
undertemperature/overtemperature alarm, intended for use
in personal computers and other systems requiring thermal
monitoring and management. The device can measure the
temperature of a microprocessor using a diode-connected
PNP transistor, which can be provided on-chip with the
Pentium® III or similar processors, or can be a low cost discrete
NPN/PNP device, such as the 2N3904/2N3906. A novel
measurement technique cancels out the absolute value of the
transistor’s base emitter voltage so that no calibration is
required. The second measurement channel measures the
output of an on-chip temperature sensor to monitor the
temperature of the device and its environment.
The ADM1021A communicates over a two-wire serial interface
compatible with SMBus standards. Undertemperature and
overtemperature limits can be programmed into the device over
the serial bus, and an ALERT output signals when the on-chip
or remote temperature is out of range. This output can be used
as an interrupt or as an SMBus alert.
FUNCTIONAL BLOCK DIAGRAM
ON-CHIP
TEMPERATURE
SENSOR
LOCAL TEMPERATURE
VALUE REGISTER
D+ 3
D– 4
ANALOG MUX
A-TO-D
CONVERTER
BUSY
RUN/STANDBY
REMOTE TEMPERATURE
VALUE REGISTER
EXTERNAL DIODE OPEN-CIRCUIT
LOCAL TEMPERATURE
LOW LIMIT COMPARATOR
LOCAL TEMPERATURE
HIGH LIMIT COMPARATOR
REMOTE TEMPERATURE
LOW LIMIT COMPARATOR
REMOTE TEMPERATURE
HIGH LIMIT COMPARATOR
STATUS REGISTER
ADDRESS POINTER
REGISTER
ONE-SHOT
REGISTER
CONVERSION RATE
REGISTER
LOCAL TEMPERATURE
LOW LIMIT REGISTER
LOCAL TEMPERATURE
HIGH LIMIT REGISTER
REMOTE TEMPERATURE
LOW LIMIT REGISTER
REMOTE TEMPERATURE
HIGH LIMIT REGISTER
CONFIGURATION
REGISTER
INTERRUPT
MASKING
15 STBY
11 ALERT
ADM1021A
SMBUS INTERFACE
125789
NC VDD NC GND GND NC
13
NC
16
NC
12
SDATA
14
SCLK
10
ADD0
6
ADD1
Figure 1.
1Protected by U.S. Patents 5,195,827; 5,867,012; 5,982,221; 6,097,239; 6,133,753; 6,169,442; other patents pending.
NC = NO CONNECT
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.






ADM1021A Datasheet, Funktion
ADM1021A
TYPICAL PERFORMANCE CHARACTERISTICS
20
15
D+ TO GND
10
5
0
–5
–10
D+ TO VDD
–15
–20
–25
–30
1
10
LEAKAGE RESISTANCE (MΩ)
100
Figure 4. Temperature Error vs. PC Board Track Resistance
5
4
250mV p-p REMOTE
3
2
100mV p-p REMOTE
1
0
100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 5. Temperature Error vs. Power Supply Noise Frequency
9
100mV p-p
8
7
6
5
4
3
50mV p-p
2
1
25mV p-p
0
1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 6. Temperature Error vs. Common-Mode Noise Frequency
3
2
UPPER SPEC LEVEL
1
0 DEV10
–1
LOWER SPEC LEVEL
–2
–3
50 60 70 80 90 100 110 120
TEMPERATURE (°C)
Figure 7. Temperature Error vs. Pentium III Temperature
14
12
10
8
6
4
2
0
–2
2 4 6 8 10 12 14 16 18 20 22 24
CAPACITANCE (nF)
Figure 8. Temperature Error vs. Capacitance Between D+ and D−
70
60
50
40
VDD = 3.3V
30
20
10
VDD = 5V
0
1 5 10 25 50 75 100 250 500 750 1000
SCLK FREQUENCY (kHz)
Figure 9. Standby Supply Current vs. Clock Frequency
Rev. F | Page 6 of 20

6 Page









ADM1021A pdf, datenblatt
ADM1021A
LIMIT REGISTERS
The ADM1021A has four limit registers to store local and
remote and high and low temperature limits. These registers
can be written to and read back over the SMBus. The high limit
registers perform a > comparison, while the low limit registers
perform a < comparison. For example, if the high limit register
is programmed as a limit of 80° C, measuring 81°C results in
an alarm condition. Even though the temperature measurement
range is from 0° to 127°C, it is possible to program the limit
register with negative values. This is for backwards compati-
bility with the ADM1021.
OFFSET REGISTER
An offset register is provided at Address 0x11. This allows the
user to remove errors from the measured remote temperature.
These errors can be introduced by clock noise and PCB track
resistance. See Table 9 for an example of offset values.
The offset value is stored as an 8-bit, twos complement value.
The value of the offset is negative if the MSB of Register 0x11
is 1, and is positive if the MSB of Register 0x11 is 0. This value is
added to the remote temperature. The offset register defaults to
0 at power-up. The offset register range is −128°C to +127°C.
Table 9. Offset Values
Offset
Register
(0x11)
1111 1100
1111 1111
0000 0000
0000 0001
0000 0100
Offset
Value
−4°C
−1°C
0°C
+1°C
+4°C
Remote
Temperature
(With
Offset)
14°C
17°C
18°C
19°C
22°C
Remote
Temperature
(Without
Offset)
18°C
18°C
18°C
18°C
18°C
ONE-SHOT REGISTER
The one-shot register is used to initiate a single conversion and
comparison cycle when the ADM1021A is in standby mode,
after which the device returns to standby. This is not a data
register as such, and it is the write operation that causes the
one-shot conversion. The data written to this address is
irrelevant and is not stored.
SERIAL BUS INTERFACE
Control of the ADM1021A is carried out via the serial bus. The
ADM1021A is connected to this bus as a slave device, under the
control of a master device. Note that the SMBus and SCL pins
are three-stated when the ADM1021A is powered down and
will not pull down the SMBus.
ADDRESS PINS
In general, every SMBus device has a 7-bit device address
(except for some devices that have extended 10-bit addresses).
When the master device sends a device address over the bus,
the slave device with that address responds.
The ADM1021A has two address pins, ADD0 and ADD1, to
allow selection of the device address so that several
ADM1021As can be used on the same bus, and/or to avoid
conflict with other devices. Although only two address pins
are provided, these are three-state and can be grounded, left
unconnected, or tied to VDD so that a total of nine different
addresses are possible, as shown in Table 10.
It should be noted that the state of the address pins is only
sampled at power-up, so changing them after power-up has
no effect.
Table 10. Device Addresses
ADD01
ADD11
Device Address
0 0 0011 000
0 NC 0011 001
0 1 0011 010
NC 0
0101 001
NC NC 0101 010
NC 1
0101 011
1 0 1001 100
1 NC 1001 101
1 1 1001 110
1ADD0, ADD1 sampled at power-up only.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDATA, while the serial clock line SCLK remains
high. This indicates that an address/data stream will
follow. All slave peripherals connected to the serial bus
respond to the START condition and shift in the next
eight bits, consisting of a 7-bit address (MSB first) plus an
R/W bit, which determines the direction of the data
transfer, that is, whether data will be written to or read
from the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the Acknowledge Bit. All other devices on the bus now
remain idle while the selected device waits for data to be
read from or written to it. If the R/W bit is a 0, the master
writes to the slave device. If the R/W bit is a 1, the master
reads from the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and
remain stable during the high period, because a low-to-
high transition when the clock is high can be interpreted
as a stop signal. The number of data bytes that can be
transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave
devices can handle.
Rev. F | Page 12 of 20

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