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ADV476 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV476
Beschreibung CMOS Monolithic 256x18 Color Palette RAM-DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
ADV476 Datasheet, Funktion
a
CMOS Monolithic 256؋18
Color Palette RAM-DAC
ADV476
FEATURES
Personal System/2* and VGA* Compatible
Plug-in Replacement for INMOS 171/176
66 MHz Pipelined Operation
Three 6-Bit D/A Converters
256؋18 Color Palette RAM
RS-343A/RS-170 Compatible Outputs
Blank on All Three Channels
Standard MPU Interface
Asynchronous Access to All Internal Registers
؉5 V CMOS Monolithic Construction
Low Power Dissipation
Standard 28-Pin, 0.6" DIP and 44-Pin PLCC
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
66 MHz
50 MHz
35 MHz
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The ADV476 (ADV®) is a pin compatible and software compat-
ible RAM-DAC designed specifically for VGA and Personal
System/2 color graphics.
The ADV476 is a complete analog output RAM-DAC on a
single monolithic chip. The part contains a 256ϫ18 color
lookup table, a pixel mask register as well as a triple 6-bit video
D/A converter. The ADV476 is capable of simultaneously dis-
playing up to 256 colors, from a total color palette of 262,144
addressable colors.
The on-chip asynchronous MPU bus allows access to the color
lookup table without affecting the input video data via the pixel
port. The pixel read mask register provides a convenient way of
altering the displayed colors without updating the color lookup
table. The ADV476 is capable of generating RGB video output
signals which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.
The ADV476 is fabricated in a +5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with low
power dissipation and small board area. The part is packaged in
a 0.6", 28-pin DIP and a 44-pin PLCC.
PRODUCT HIGHLIGHTS
1. Standard video refresh rates, 35 MHz, 50 MHz and
66 MHz.
2. Fully compatible with VGA and Personal System/2 color
graphics.
3. Guaranteed monotonic. Integral and differential linearity
guaranteed to be a maximum of ± 1 LSB.
4. Low glitch energy, 75 pV secs.
*Personal System/2 and VGA are trademarks of International Business
Machines Corp.
ADV is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






ADV476 Datasheet, Funktion
ADV476
MPU Interface
As illustrated in the functional block diagram, the ADV476 sup-
ports a standard MPU bus interface, allowing the MPU direct
access to the color palette RAM.
The RS0 and RS1 control inputs specify whether the MPU is
accessing the address register or the color palette RAM, as
shown in Table I. The 8-bit address register is used to address
the color palette RAM, eliminating the requirement for external
address multiplexers.
Table I. Control Input Truth Table
RS1 RS0 Addressed by MPU
00
11
01
10
Pixel Address Register (RAM Write Mode)
Pixel Address Register (RAM Read Mode)
Color Palette RAM
Pixel Read Mask Register
To write color data, the MPU writes to the address register with
the 8-bit address of the color palette RAM location which is to
be modified. The MPU performs three successive write cycles
(six bits of red data, six bits of green data and six bits of blue
data). During the blue write cycle, the three bytes of color infor-
mation are concatenated into an 18-bit word and written to the
location specified by the address register. The address register
then automatically increments to the next location which the
MPU may modify by simply writing another sequence of red,
green and blue data.
To read back color data, the MPU loads the address register
with the address of the color palette RAM location to be read.
The MPU performs three successive read cycles (6 bits each of
red, green and blue data). Following the blue read cycle, the
address register increments to the next location which the MPU
may read by simply reading another sequence of red, green and
blue data.
This 6-bit color data is right justified, i.e., the lower six bits of
the data bus with D0 being the LSB and D5 the MSB. D6 and
D7 are ignored during a color write cycle and are set to zero
during a color read cycle.
During color palette RAM access, the address register resets to
00H following a blue read or write operation to RAM location
FFH.
The MPU interface operates asynchronously to the pixel clock.
Data transfers between the color palette RAM and the color
registers (R, G, and B in the block diagram) are synchronized by
internal logic, and occur in the period between MPU accesses.
Color (RGB) data is normally loaded to the color palette RAM
during video screen retrace, i.e., during the video waveform
blanking period, see Figure 5.
To keep track of the red, green and blue read/write cycles, the
address register has two additional bits (ADDRa, ADDRb) that
count modulo three, as shown in Table II. They are reset to
zero when the MPU writes to the address register, and are not
reset to zero when the MPU reads the address register. The
MPU does not have access to these bits. The other eight bits of
the address register, incremented following a blue read or write
cycle, (ADDR0–7) are accessible to the MPU, and are used to
address color palette RAM locations, as shown in Table III.
ADDR0 is the LSB when the MPU is accessing the RAM. The
MPU may read the address register at any time without modify-
ing its contents or the existing read/write mode.
Figure 1 illustrates the MPU read/write timing and Table III
shows the associated functional instructions.
Table II. Address Register (ADDR) Operation
Value
RS1 RS0 Addressed by MPU
ADDRa,b (Counts Modulo 3)
00
01
10
Red Value
Green Value
Blue Value
ADDR0–7 (Counts Binary)
00H–FFH 0
1 Color Palette RAM
Table III. Truth Table for Read/Write Operations
RD WR RS0 RS1 ADDRa ADDRb Operation Performed
10 0 0 X
10 1 0 0
10 1 0 0
10 1 0 1
X
0
1
0
Write Address Register;
Write Red Value;
Write Green Value;
Write Blue Value;
D0–D7ADDR0–7
0ADDRa,b
Increment ADDRa–b
Increment ADDRa–b
Modify RAM Location
Increment ADDR0–7
Increment ADDRa–b
01 1 1 X
01 1 0 0
01 1 0 0
01 1 0 1
X
0
1
0
Read Address Register;
Read Red Value;
Read Green Value;
Read Blue Value;
ADDR0–7D0–D7
Increment ADDRa–b
Increment ADDRa–b
Increment ADDR0–7
Increment ADDRa–b
00
XXX
X
Invalid Operation
–6– REV. B

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