ADV453 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV453
Beschreibung CMOS 66MHz Monolithic 256 x 324 Color Palette RAM-DAC
Hersteller Analog Devices
Logo Analog Devices Logo 

Gesamt 12 Seiten
ADV453 Datasheet, Funktion
CMOS 66 MHz Monolithic 256؋24
Color Palette RAM-DAC
66 MHz Pipelined Operation
Triple 8-Bit D/A Converters
256؋24 Color Palette RAM
3؋24 Overlay Registers
RS-343A/RS-170 Compatible Outputs
؉5 V CMOS Monolithic Construction
40-Pin DIP or Small 44-Pin PLCC Package
Power Dissipation: 1000 mW
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Desktop Publishing
66 MHz
40 MHz
The ADV453 is a complete analog video output RAM-DAC on
a single monolithic chip. It is specifically designed for high reso-
lution color graphics systems. The part contains a 256 ϫ 24
color lookup table, a 3 ϫ 24 overlay palette as well as triple 8-bit
video D/A converters. The ADV453 is capable of simulta-
neously displaying up to 259 colors, 256 from the lookup table
and three from the overlay registers, out of a total color palette
of 16.8 million addressable colors.
The three overlay registers allow for implementation of overlay-
ing cursors, pull down menus and grids. There is an indepen-
dent, asynchronous MPU bus which allows access to the color
lookup table without affecting the input of video data via the
pixel port. The ADV453 is capable of generating RGB video
output signals which are compatible with RS-343A and RS-170
video standards, without requiring external buffering.
The ADV453 is fabricated in a +5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with low
power dissipation. The part is packaged in both a 0.6", 40-pin
DIP and a 44-pin plastic leaded (J-lead) chip carrier, PLCC.
1. Fast video refresh rate, 66 MHz.
2. Compatible with a wide variety of high resolution color
graphics systems including VGA* and Macintosh II.**
3. Three overlay registers allow for implementation of overlay-
ing cursors, pull down menus and grids.
4. Guaranteed monotonic. Integral and differential nonlineari-
ties guaranteed to be a maximum of ± 1 LSB.
5. Low glitch energy, 50 pV secs.
**VGA is a trademark of International Business Machines Corp.
**Macintosh II is a registered trademark of Apple Computer Inc.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

ADV453 Datasheet, Funktion
Blanking Level
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.
Color Video (RGB)
This usually refers to the technique of combining the three pri-
mary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Sync Signal (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different lev-
els while a 6-bit DAC contains 64.
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Sync Level
The peak level of the SYNC signal.
Video Signal
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
MPU Interface
As illustrated in the functional block diagram, the ADV453 sup-
ports a standard MPU bus interface, allowing the MPU direct
access to the color palette RAM and overlay color registers. The
color palette RAM and overlay color registers can be accessed
only when CS is low. The Pixel and Overlay Select inputs are
disabled while CS is low.
The C0 and C1 control inputs specify whether the MPU is ac-
cessing the address register, the color palette RAM or the over-
lay registers, as shown in Table I. The 8-bit address register is
used to address the color palette RAM and overlay registers,
eliminating the requirement for external address multiplexers.
Table I. Control Input Truth Table
CS C1 C0 Addressed by MPU
0 X 0 Address Register
0 0 1 Color Palette RAM
0 1 1 Overlay Register
To write color data, the MPU writes to the address register with
either the address of the color palette RAM location or the ad-
dress of the overlay register which is to be modified. The MPU
performs three successive write cycles (8 bits of red data, 8 bits
of green data and 8 bits of blue data). The color data is diverted
to either the color palette RAM or the overlay registers, as deter-
mined by C0 and C1. During the blue write cycle, the three
bytes of color information are concatenated into a 24-bit word
and written to the location specified by the address register. The
address register then automatically increments to the next loca-
tion which the MPU may modify by simply writing another se-
quence of red, green and blue data.
To read back color data, the MPU loads the address register
(selecting RAM or overlay read mode) with the address of the
color palette RAM location or overlay register to be read. The
MPU performs three successive read cycles (8 bits each of red,
green and blue data), using C0 and C1 to select either the color
palette RAM or the overlay registers. Following the blue read
cycle, the address register increments to the next location which
the MPU may read by simply reading another sequence of red,
green and blue data.
When CS is low i.e., during MPU read/write cycles, the video
outputs are forced to the black level. During color palette RAM
access, the address register resets to 00H following a blue read
or write operation to RAM location FFH.
–6– REV. B

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