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PDF AK93C85A Data sheet ( Hoja de datos )
| Número de pieza | AK93C85A | |
| Descripción | 16K / 32K / 64KBIT SERIAL CMOS EEPROM | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK93C85A/95A/10A]
AK93C85A / 95A / 10A
16K / 32K / 64Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY
READ/WRITE NON-VOLATILE MEMORY
WIDE VCC OPERATION Vcc = 1.8V 5.5V
AK93C85A 16384 bits, 1024 16 organization
AK93C95A 32768 bits, 2048 16 organization
AK93C10A 65536 bits, 4096 16 organization
SERIAL INTERFACE
- Interfaces with popular microcontrollers and standard microprocessors
LOW POWER CONSUMPTION
- 0.4mA max. Read Operation
- 0.8A Max. Standby
HIGH RELIABILITY
-Endurance
: 100K cycles
-Data Retention : 10 years
Automatic address increment (READ)
Automatic write cycle time-out with auto-ERASE (Max. 8ms : VCC=4.5V 5.5V)
Busy/Ready status signal
Software controlled write protection
IDEAL FOR LOW DENSITY DATA STORAGE
- Low cost, space saving, 8-pin package
DAM02E-01
Block Diagram
-1-
1999/10
1 page  
ASAHI KASEI
[AK93C85A/95A/10A]
Write
The write instruction is followed by 16 bits of data to be written into the specified address.
AK93C85A : After the last bit of data is put on the DI pin, the CS pin must be brought low
before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming
cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns
(Tcs).
AK93C95A/10A : The self-timed programming cycle is initiated on the rising edge of the SK
clock as the last data bit (D0) is clocked in. The DO indicates the Busy/Ready status of the chip after the self-
timed programming cycle is initiated.
The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes
into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction
is given to the part.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the
address specified in the instruction has been written with the new data pattern contained in the instruction and
the part is ready for a next instruction.
DAM02E-01
-5-
1999/10
5 Page 
ASAHI KASEI
Synchronous Data timing
[AK93C85A/95A/10A]
The Start of Instruction
The End of Instruction
DAM02E-01
- 11 -
1999/10
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet AK93C85A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AK93C85A | 16K / 32K / 64KBIT SERIAL CMOS EEPROM | Asahi Kasei Microsystems |
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