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PDF AK4393 Data sheet ( Hoja de datos )

Número de pieza AK4393
Descripción ADVANCED MULTI-BIT 96KHZ 24-BIT DAC
Fabricantes Asahi Kasei Microsystems 
Logotipo Asahi Kasei Microsystems Logotipo



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[AK4393]
AK4393
Advanced Multi-Bit 96kHz 24-Bit ΔΣ DAC
GENERAL DESCRIPTION
The AK4393 is a high performance stereo DAC for the 96kHz sampling mode of DAT, DVD including a
24bit digital filter. The AK4393 introduces the advanced multi-bit system for ΔΣ modulator. This new
architecture achieves the wider dynamic range, while keeping much the same superior distortion
characteristics as conventional Single-Bit way. In the AK4393, the analog outputs are filtered in the
analog domain by switched-capacitor filter (SCF) with high tolerance to clock jitter. The analog outputs
are full differential output, so the device is suitable for hi-end applications. The operating voltages support
analog 5V and digital 3.3V, so it is easy to I/F with 3.3V logic IC.
FEATURES
128x Oversampling
Sampling Rate up to 108kHz
24Bit 8x Digital Filter
Ripple: ±0.005dB, Attenuation: 75dB
High Tolerance to Clock Jitter
Low Distortion Differential Output
Digital de-emphasis for 32, 44.1, 48 & 96kHz sampling
Soft Mute
THD+N: -100dB
DR, S/N: 120dB
I/F format:
MSB justified, 16/20/24bit LSB justified, I2S
Master Clock: Normal Speed: 256fs, 384fs, 512fs or 768fs
Double Speed: 128fs, 192fs, 256fs or 384fs
Power Supply: 4.75 to 5.25V (Analog), 3 to 5.25V (Digital)
Small Package: 28pin SSOP
DIF0 DIF1 DIF2 DVDD DVSS
DEM0 DEM1 AVDD AVSS
LRCK
BICK
SDATA
PDN
SMUTE
DFS
Audio Data
Interface
De-emphasis
Control
De-emphasis
Soft Mute
De-emphasis
Soft Mute
8x
Interpolator
ΔΣ
Modulator
8x
Interpolator
ΔΣ
Modulator
SCF
SCF
Control Register
Clock Divider
BVSS
VCOM
AOUTL+
AOUTL-
AOUTR+
AOUTR-
CSN CCLK CDTI P/S MCLK CKS0 CKS1 CKS2 VREFH VREFL
M0039-E-03
-1-
2012/01

1 page




AK4393 pdf
[AK4393]
ANALOG CHARACTERISTICS
(Ta = 25°C; AVDD = 5V, DVDD = 3.3V; AVSS, BVSS, DVSS = 0V, VREFH = AVDD, VREFL = AVSS;
fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement Bandwidth = 20Hz~20kHz;
RL 600Ω; External circuit: Figure 11; unless otherwise specified)
Parameter
min typ max Unit
Resolution
24 Bits
Dynamic Characteristics (Note 5)
THD+N
fs=44.1kHz
BW=20kHz
0dBFS
-60dBFS
-100 -90 dB
-53 - dB
fs=96kHz
BW=40kHz
0dBFS
-60dBFS
-97 -86 dB
-51 - dB
Dynamic Range
(-60dBFS with A-weighted)
fs=44.1kHz (Note 6)
(Note 7)
fs=96kHz
(Note 7)
112
-
111
-
117
120
116
118
dB
dB
dB
dB
S/N (A-weighted
fs=44.1kHz (Note 8)
(Note 7)
fs=96kHz
(Note 7)
112
-
111
-
117
120
116
118
dB
dB
dB
dB
Interchannel Isolation (1kHz)
100 120
dB
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Output Voltage
Load Resistance
0.15 0.3 dB
(Note 9)
20 - ppm/°C
(Note 10)
±2.25
±2.4
±2.55
Vpp
(Note 11)
600
Ω
Output Current
3.5 mA
Power Supplies
Power Supply Current
Normal Operation (PDN = “H”)
AVDD
60 - mA
DVDD(fs=44.1kHz)
3 - mA
DVDD(fs=96kHz)
5 - mA
AVDD + DVDD
90 mA
Power-Down Mode (PDN = “L”)
AVDD + DVDD
(Note 12)
10 50 µA
Power Supply Rejection
(Note 13)
50
dB
Notes: 5. At 44.1kHz, measured by Audio Precision, System Two. Averaging mode.
At 96kHz, measured by ROHDE & SCHWARZ, UPD. Averaging mode.
Refer to the eva board manual.
6. 101dB at 16bit data and 116dB at 20bit data.
7. By Figure12. External LPF Circuit Example 2.
8. S/N does not depend on input bit length.
9. The voltage on (VREFH-VREFL) is held +5V externally.
10. Full-scale voltage (0dB). Output voltage scales with the voltage of (VREFH-VREFL).
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5.
11. For AC-load. 1kΩ for DC-load.
12. In the power-down mode. P/S = DVDD, and all other digital input pins including clock pins (MCLK, BICK
and LRCK) are held DVSS.
13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V.
M0039-E-03
-5-
2012/01

5 Page





AK4393 arduino
[AK4393]
„ Audio Serial Interface Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the
DIF0-2 as shown in Table 5. In all formats the serial data is MSB-first, 2's compliment format and is latched on the rising
edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
Mode
0: 16bit LSB Justified
1: 20bit LSB Justified
2: 24bit MSB Justified
3: I2S Compatible
4: 24bit LSB Justified
BICK
32fs
40fs
48fs
48fs
48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Table 5. Audio Data Formats
LRCK
BICK
(32fs)
SDATA
Mode 0
BICK
(64fs)
SDATA
Mode 0
01
10 11 12 13 14 15 0 1
15 14
01
6 5 4 3 2 1 0 15 14
14 15 16 17
31 0 1
Don’t care
15 14
15:MSB, 0:LSB
Lch Data
0 Don’t care
10 11 12 13 14 15 0 1
6 5 4 3 2 1 0 15 14
14 15 16 17
31 0 1
15 14
0
Rch Data
Figure 1. Mode 0 Timing
LRCK
BICK
(64fs)
SDATA
Mode 1
SDATA
Mode 4
01
8 9 10 11 12
Don’t care
19:MSB, 0:LSB
19
Don’t care 23 22 21 20 19
23:MSB, 0:LSB
Lch Data
31 0 1
8 9 10 11 12
0 Don’t care
19
0 Don’t care 23 22 21 20 19
Rch Data
31 0 1
0
0
Figure 2. Mode 1,4 Timing
M0039-E-03
- 11 -
2012/01

11 Page







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