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AK2305 Schematic ( PDF Datasheet ) - Asahi Kasei Microsystems

Teilenummer AK2305
Beschreibung Dual PCM CODEC
Hersteller Asahi Kasei Microsystems
Logo Asahi Kasei Microsystems Logo 




Gesamt 30 Seiten
AK2305 Datasheet, Funktion
ASAHI KASEI
[AK2305]
AK2305
Dual PCM CODEC for ISDN TERMINAL ADAPTER
GENERAL DESCRIPTION
AK2305 is a dual PCM CODEC-Filter most
suitable for ISDN Terminal Adapter. A-law/u-
law is selected by the internal register.
In addition to CODEC, this device has dual
DTMF receiver and External Tone Input pin.
Input/output operational amplifiers included in
this device are used for transmit/receive gain
adjustment. AK2305 has internal volume control
to attenuate signal from 0dB to –12dB by 3dB
step control which is defined by an internal
register written through the serial interface.
PCM interface of AK2305 accepts several clock
formats, which are Long Frame, Short Frame,
GCI, IDL. 64k-4096kHz clock input is available
for PCM interface.
FEATURE
- Dual PCM CODEC and Filtering systems for
ISDN Terminal Adapter
- Dual DTMF Receiver
- External Tone Input(AUX)
- Independent functions on each channel
- Frame Sync Signal(8kHz)
- Power Down Mode(Pin/Register operation)
- Mute(Pin/Register operation)
- Gain Adjustment: 0 to -12dB (3dB step)
- Selectable PCM Data Interface Timing:
Long Frame / Short Frame / GCI / IDL
- Variable PCM Data Rate:
64k x N [Hz] (64k - 4.096MHz)
- Operational Amplifier for Gain Adjustment
- A-law/u-law Register Selectable
- Serial Interface
- Power on Reset
- Single +5V ± 5% CMOS technology
- Low Power Consumption (85mW typ)
PACKAGE
- 48LQFP
9.0 x 9.0 mm (0.5mm pin pitch)
C0029-E-02
1 1999/8






AK2305 Datasheet, Funktion
ASAHI KASEI
Pin# Name
48 VFX0
47 GSX0
1 VRX0
2 VFX0
3 GSR0
10 GSR1
11 VFR1
12 VRX1
14 GSX1
13 VFX1
29 DX0
33 DR0
28 DX1
32 DR1
26 FS0
[AK2305]
PIN FUNCTION
I/O Function
I Transmit analog input. Inverting input of transmit gain adjustment
amplifier for channel 0.
O Output of transmit gain adjustment amplifier for channel 0.
O Receive analog output of SMF for channel 0. This output can drive 10k
and 50pF.
I Transmit analog input. Inverting input of transmit gain adjustment
amplifier for channel 0.
O Output of receive gain adjustment amplifier for channel 0.
O Output of receive gain adjustment amplifier for channel 1.
I Inverting input of receive gain adjustment amplifier for channel 1.
O Receive analog output of SMF for channel 1. This output can drive 10k
and 50pF.
O Output of transmit gain adjustment amplifier for channel 1.
I Transmit analog input. Inverting input of transmit gain adjustment
amplifier for channel 1.
O Serial output of PCM data of ch0.
In Long Frame / Short Frame mode, output PCM data of ch0.
In GCI / IDL mode, output PCM data of ch0 is multiplexed with ch1. The
PCM data rate is synchronized with BCLK.
See “PCM INTERFACE” from page 9.
This output remains in the high impedance state except for the period of
transmitting PCM data.
I Serial input of PCM data of ch0.
In Long Frame / Short Frame mode, input PCM data of ch0.
In GCI / IDL mode, input PCM data of ch0 is multiplexed with ch1. The
PCM data rate is synchronized with BCLK.
See “PCM INTERFACE” from page 9.
O Serial output of PCM data of ch1.
In Long Frame / Short Frame mode, output PCM data of ch1.
The PCM data rate is synchronized with BCLK.
See “PCM INTERFACE” from page 9.
This output remains in the high impedance state except for the period of
transmitting PCM data.
In 2ch multiplexd mode, this pin remains in the high impedance state.
O Serial input of PCM data of ch1.
In Long Frame / Short Frame mode, input PCM data of ch1. The PCM
data rate is synchronized with BCLK.
See “PCM INTERFACE” from page 9.
In GCI / IDL mode, this pin is pulled down to VSS.
I Frame sync input for channel 0.
FS0 must be 8KHz clock synchronized in BCLK.
C0029-E-02
6 1999/8

6 Page









AK2305 pdf, datenblatt
ASAHI KASEI
GCI(General Circuit Interface)
Interface used for ISDN. This data format is as below.
PCM data channel assignment for B1 and B2 is defined by SEL2B register.
CH0,1selection
SEL2B
0
1
CH0
B1
B2
CH1 Remarks
B2 Reset
B1
Note: BCLK is twice the PCM data rate.
BCLK is acceptable from 512kHz to 4096kHz.
INTERFACE TIMING
<2ch Multiplex>
PCM data of each channel is interfaced through DR0/DX0 pin in 8bits format.
They are accommodated in 1 frame(125us) which synchronizes with FS0.
[AK2305]
FS0
BCLK
DX0
1234567812345678
DR0
Don’t
care
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Don’t
care
B1-CHANNEL(CH0)
<SEL2B=”0”>
B2-CHANNEL(CH1)
<SEL2B=”0”>
<Non Multiplex>
Not supported.
C0029-E-02
12 1999/8

12 Page





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