Datenblatt-pdf.com


ADV7202 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7202
Beschreibung Simultaneous Sampling Video Rate Codec
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 26 Seiten
ADV7202 Datasheet, Funktion
PRELIMINARY TECHNICAL DATA
a
Simultaneous Sampling
Video Rate Codec
Preliminary Technical Data
ADV7202
FEATURES
Four 10-Bit Video DACs (4:2:2, YCrCb, RGB I/P
Supported)
10-Bit Video Rate Digitization at Up to 54 Mhz
AGC Control (؎6 dB)
Front-End 3-Channel Clamp Control
Up to Five CVBS Input Channels, Two Component YUV,
Three S-Video, or a combination of the above. Simul-
taneous Digitization of Two CVBS Input Channels.
Aux 8-Bit SAR ADC @ 843 kHz Sampling Giving up to
Eight General Purpose Inputs
I2C and SPI Compatible Interface with I2C Filter
RGB Inputs for Picture-on-Picture of the RGB DACs
APPLICATIONS
Picture-on-Picture Video Systems
Simultaneous Video Rate Processing
Hybrid Set-Top Box TV Systems
Direct Digital Synthesis/I-Q Demodulation
Image Processing
GENERAL DESCRIPTION
The ADV7202 is a video rate sampling Codec.
It has the capability of sampling up to five NTSC/PAL/SECAM
video I/P signals. The resolution on the front-end digitizer is
12 bits; 2 bits (12 dB) are used for gain and offset adjustment.
The digitizer has a conversion rate of 54 MHz.
It also has up to eight auxiliary inputs that can be sampled by
an 843 kHz SAR ADC for system monitoring, etc.
The back end consists of four 10-bit DACs that run at up to
54 MHz and can be used to output CVBS, S-Video, Component
YCrCb, and RGB.
This Codec also supports Picture-on-Picture with the 3-channel
I/P mux that also muxes to the DAC O/Ps.
The ADV7202 can operate at 3.3 V or 5 V. Its monolithic CMOS
construction ensures greater functionality with lower power
dissipation.
The ADV7202 is packaged in a small 64-lead LQFP package.
FUNCTIONAL BLOCK DIAGRAM
DOUT DAC DATA
XTAL [9:0]
[9:0]
OSD I/P "S"
AIN1P
AIN1M
AIN2P
AIN2M
AIN3P
AIN3M
AIN4P
AIN4M
AIN5P
AIN5M
AIN6P
AIN6M
I/P
MUX
SHA AND
CLAMP
SHA AND
CLAMP
SHA AND
CLAMP
MUX
ADC BLOCK
12-BIT
A/D
A/D
8-BIT 843KHz
ADV7202
ADC
DAC
LOGIC LOGIC
10-BIT
D/A
10-BIT
D/A
10-BIT
D/A
10-BIT
D/A
12C/SPI
DAC0
DAC1
DAC2
DAC3
REV. PrB
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






ADV7202 Datasheet, Funktion
PRELIMINARY TECHNICAL DATA
ADV7202–SPECIFICATIONS
3.3 V SPECIFICATIONS (AVDD/DVDD = 3.3 V ؎ 5%, VREF = 1.235 V RSET = 1.2 k, all specifications TMIN to TMAX unless otherwise noted.)
Parameter
Min Typ Max
Unit
Test Conditions
POWER REQUIREMENTS1
AVDD/DVDD
Normal Power Mode
IDAC2
IDSC3
IADC4
Sleep Mode
Current
PSU Rejection Ratio
DACs
Video ADC
Aux ADC
Power-Up Time
3.15 3.3 3.45
V
4 mA
34 mA
21 mA
100 µA
0.01
0.01
TBD
TBD
0.5
0.5
TBD
%/%
%/%
TBD
TBD
RSET = 1.2 k, RL = 300
RSET = 1.2 k, RL = 300
COMP = 0.1 µF
TBD
TBD
MPU PORT—I2C5
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
MPU PORT—SPI5, 6
SCLOCK Frequency
SCLOCK High Pulsewidth, t21
SCLOCK Low Pulsewidth, t22
SI Data Setup Time, t20
SI Data Hold Time, t19
RESET Low Time
0
0.6
1.3
0.6
0.6
100
0.6
TBD
TBD
TBD
TBD
TBD
100
400
300
300
TBD
TBD
TBD
TBD
TBD
kHz
µs
µs
µs
µs
ns
ns
ns
µs
kHz
kHz
ns
ns
ns
ns
After this period the first clock is
generated.
Relevant for Repeated Start Condition
NOTES
1All DACs and ADCs on.
2IDAC is the DAC supply current.
3IDSC is the digital core supply current.
4IADC is the ADC supply current.
5TTL input values are 0 V to 3 V, with input rise/fall times 3 ns, as measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
6See SPI timing diagram Figures 10 and 11.
Specifications subject to change without notice.
–6– REV. PrB

6 Page









ADV7202 pdf, datenblatt
ADV7202
PRELIMINARY TECHNICAL DATA
XTAL0
DAC_DATA [9:0] CR Y CB Y CR Y CB
SYNC_OUT
Figure 3. SYNC_OUT Output Timing, YCrCb Input
MPU PORT DESCRIPTION
The ADV7202 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two inputs,
Serial Data (SDA) and Serial Clock (SCL), carry information
between any device connected to the bus. Each slave device is
recognized by a unique address. The ADV7202 has four pos-
sible slave addresses for both read and write operations. These
are unique addresses for each device and are illustrated in
Figure 4. The LSB sets either a read or write operation. Logic
Level “1” corresponds to a read operation, while Logic Level
“0” corresponds to a write operation. A1 is set by setting the
ALSB pin of the ADV7202 to Logic Level “0” or Logic Level
“1.” When ALSB is set to “0,” there is greater input bandwidth
on the I2C lines, which allows high-speed data transfers on this
bus. When ALSB is set to “1,” there is reduced input band-
width on the I2C lines, which means that pulses of less than
50 ns will not pass into the I2C internal controller. This mode is
recommended for noisy systems.
0 0 1 0 1 1 A1 X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0 DISABLED
1 ENABLED
Figure 4. Slave Address
To control the various devices on the bus, the following proto-
col must be followed. First the master initiates a data transfer by
establishing a Start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the Start
condition and shift the next eight bits (7-bit address + R/W bit).
The bits are tranferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
Acknowledge Bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition
is where the device monitors the SDA and SCL lines waiting for
the Start condition and the correct transmitted address. The R/W
bit determines the direction of the data.
A Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7202A acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. It interprets the first byte as the
device address and the second byte as the starting subaddress.
The subaddresses auto-increment, allowing data to be written to
or read from the starting subaddress. A data transfer is always
terminated by a Stop condition. The user can access any unique
subaddress register on a one-by-one basis without updating all
the registers.
Stop and Start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period, the
user should only issue one Start condition, one Stop condition,
or a single Stop condition followed by a single Start condition. If
an invalid subaddress is issued by the user, the ADV7202 will
not issue an acknowledge and will return to the idle condition. If
in auto-increment mode, the user exceeds the highest subaddress,
the following action will be taken:
1. In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is where the SDA line is not
pulled low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7202, and the part will return to the
idle condition.
Figure 5 illustrates an example of data transfer for a read
sequence and the Start and Stop conditions.
SDATA
SCLOCK S 1–7 8 9
1–7 8 9
START ADDR R/W ACK SUBADDRESS ACK
1–7 8 9
P
DATA
ACK STOP
Figure 5. Bus Data Transfer
–12–
REV. PrB

12 Page





SeitenGesamt 26 Seiten
PDF Download[ ADV7202 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADV7202Simultaneous Sampling Video Rate CodecAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche