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PDF ADV7177 Data sheet ( Hoja de datos )
| Número de pieza | ADV7177 | |
| Descripción | Integrated Digital CCIR-601 to PAL/NTSC Video Encoder | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Integrated Digital CCIR-601
to PAL/NTSC Video Encoder
ADV7177/ADV7178
FEATURES
ITU-R BT601/656 YCrCb to PAL/NTSC video encoder
High quality, 9-bit video DACs
Integral nonlinearity <1 LSB at 9 bits
NTSC-M, PAL-M/N, PAL-B/D/G/H/I
Single 27 MHz crystal/clock required (±2 oversampling)
75 dB video SNR
32-bit direct digital synthesizer for color subcarrier
Multistandard video output support:
Composite (CVBS)
Component S-video (Y/C)
Component YUV or RGB
Video input data port supports:
CCIR-656 4:2:2 8-bit parallel input format
4:2:2 16-bit parallel input format
Full video output drive or low signal drive capability
34.7 mA max into 37.5 Ω (doubly terminated 75 R)
5 mA min with external buffers
Programmable simultaneous composite and S-VHS
(VHS) Y/C or RGB (SCART)/YUV video outputs
Programmable luma filters (low-pass/notch/extended)
Programmable VBI (vertical blanking interval)
Programmable subcarrier frequency and phase
Programmable luma delay
Individual on/off control of each DAC
CCIR and square pixel operation
Color-signal control/burst-signal control
Interlaced/noninterlaced operation
Complete on-chip video timing generator
OSD support (ADV7177 only)
Programmable multimode master/slave operation
Macrovision AntiTaping Rev. 7.01 (ADV7178 only)1
Closed captioning support
On-board voltage reference
2-wire serial MPU interface (I2C®-compatible)
Single-supply 5 V or 3 V operation
Small 44-lead MQFP package
Synchronous 27 MHz/13.5 MHz clock output
APPLICATIONS
MPEG-1 and MPEG-2 video, DVD, digital satellite,
cable systems (set-top boxes/IRDs), digital TVs,
CD video/karaoke, video games, PC video/multimedia
1 The Macrovision anticopy process is licensed for noncommercial home use
only, which is its sole intended use in the device. Please contact sales office
for latest Macrovision version available. ITU-R and CCIR are used inter-
changeably in this document (ITU-R has replaced CCIR recommendations).
FUNCTIONAL BLOCK DIAGRAM
VAA
ADV7177
ONLY
OSD_EN
OSD_0
OSD_1
OSD_2
COLOR
DATA
P7–P0
P15–P8
HSYNC
FIELD/VSYNC
BLANK
ADV7177/ADV7178
8
4:2:2 TO
4:4:4 8
INTER-
POLATOR
8
8
YCrCb
TO 8
YUV
MATRIX
8
ADD 8
SYNC
ADD 8
BURST
ADD 8
BURST
INTER- 8
POLATOR
INTER- 8
POLATOR
INTER- 8
POLATOR
VIDEO TIMING
GENERATOR
I2C MPU PORT
YUV TO
RBG
MATRIX
Y
LOW-PASS
FILTER
U9
LOW-PASS
FILTER
V9
LOW-PASS
FILTER
9
99
SIN/COS
DDS BLOCK
9 9-BIT
DAC
9 9-BIT
DAC
9 9-BIT
DAC
DAC A
(PIN 31)
DAC B
(PIN 27)
DAC C
(PIN 26)
VOLTAGE
REFERENCE
CIRCUIT
VREF
RSET
COMP
CLOCK CLOCK CLOCK/2 RESET SCLOCK SDATA ALSB
GND
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
ADV7177/ADV7178
SPECIFICATIONS
5 V SPECIFICATIONS
VAA = 5 V ± 5%,1 VREF = 1.235 V, RSET = 300 Ω. All specifications TMIN to TMAX2, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE3
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS3
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN4
Input Current, IIN5
Input Capacitance, CIN
DIGITAL OUTPUTS3
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
ANALOG OUTPUTS3
Output Current6
Output Current7
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
VOLTAGE REFERENCE3
Reference Range, VREF
POWER REQUIREMENTS3, 8
VAA
Low Power Mode
IDAC (max)9
IDAC (min)9
ICCT10
Power-Supply Rejection Ratio
Conditions1
Min Typ
Guaranteed monotonic
VIN = 0.4 V or 2.4 V
VIN = 0.4 V or 2.4 V
ISOURCE = 400 µA
ISINK = 3.2 mA
RSET = 300 Ω, RL = 75 Ω
IOUT = 0 mA
IVREFOUT = 20 µA
COMP = 0.1 µF
2
10
2.4
10
16.5 17.35
5
0.6
0
15
1.112
4.75
1.235
5.0
62
25
100
0.01
Max
9
±1.0
±1.0
0.8
±1
± 50
0.4
10
18.5
5
1.4
30
1.359
5.25
150
0.5
Unit
Bits
LSB
LSB
V
V
µA
µA
pF
V
V
µA
pF
mA
mA
%
V
kΩ
pF
V
V
mA
mA
mA
%/%
1 The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2 Temperature range TMIN to TMAX: 0°C to 70°C.
3 Guaranteed by characterization.
4 All digital input pins except pins RESET, OSD0, and CLOCK.
5 Excluding all digital input pins except pins RESET, OSD0, and CLOCK.
6 Full drive into 75 Ω load.
7 Minimum drive current (used with buffered/scaled output load).
8 Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C.
9 IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 18.5 mA output per DAC) to drive all three DACs. Turning off individual DACs
reduces IDAC correspondingly.
10 ICCT (circuit current) is the continuous current required to drive the device.
Rev. C | Page 5 of 44
5 Page 
SDATA
SCLOCK
t3 t5 t3
t6 t1
t2 t7
t4
Figure 2. MPU Port Timing Diagram
CLOCK
CONTROL
I/PS
HSYNC,
FIELD/VSYNC,
BLANK
PIXEL INPUT
DATA
CONTROL
O/PS
HSYNC,
FIELD/VSYNC,
BLANK
t9 t10
t12
Cb Y Cr Y
t11
Cb
t13
Y
t14
Figure 3. Pixel and Control Data Timing Diagram
CLOCK
t16 t17
CLOCK/2
CLOCK
CLOCK/2
t16
CLOCK
OSD_EN
OSD0–2
t18
t17
Figure 4. Internal Timing Diagram
t19
Figure 5. OSD Timing Diagram
ADV7177/ADV7178
t8
Rev. C | Page 11 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADV7177.PDF ] | |
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