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Am29F016B-120DPC1 Schematic ( PDF Datasheet ) - Advanced Micro Devices

Teilenummer Am29F016B-120DPC1
Beschreibung 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only/ Sector Erase Flash Memory-Die Revision 1
Hersteller Advanced Micro Devices
Logo Advanced Micro Devices Logo 




Gesamt 38 Seiten
Am29F016B-120DPC1 Datasheet, Funktion
PRELIMINARY
Am29F016B
16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 V ± 10%, single power supply operation
— Minimizes system level power requirements
s Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29F016 device
s High performance
— Access times as fast as 70 ns
s Low power consumption
— 25 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access
time to active mode)
s Flexible sector architecture
— 32 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased
— Supports full chip erase
— Group sector protection:
A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code
changes in previously locked sectors
s Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
s Minimum 1,000,000 program/erase cycles per
sector guaranteed
s Package options
— 48-pin and 40-pin TSOP
— 44-pin SO
s Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
s Data# Polling and toggle bits
— Provides a software method of detecting
program or erase cycle completion
s Ready/Busy# output (RY/BY#)
— Provides a hardware method for detecting
program or erase cycle completion
s Erase Suspend/Erase Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
s Hardware reset pin (RESET#)
— Resets internal state machine to the read mode
Publication# 21444 Rev: B Amendment/+2
Issue Date: April 1998






Am29F016B-120DPC1 Datasheet, Funktion
PRELIMINARY
CONNECTION DIAGRAMS
NC 1
RESET# 2
A11 3
A10 4
A9 5
A8 6
A7 7
A6 8
A5 9
A4 10
NC 11
NC 12
A3 13
A2 14
A1 15
A0 16
DQ0 17
DQ1 18
DQ2 19
DQ3 20
VSS 21
VSS 22
SO
44 VCC
43 CE#
42 A12
41 A13
40 A14
39 A15
38 A16
37 A17
36 A18
35 A19
34 NC
33 NC
32 A20
31 NC
30 WE#
29 OE#
28 RY/BY#
27 DQ7
26 DQ6
25 DQ5
24 DQ4
23 VCC
21444B-6
PIN CONFIGURATION
A0–A20 =
DQ0–DQ7 =
CE#
=
21 Addresses
8 Data Inputs/Outputs
Chip Enable
WE#
OE#
= Write Enable
= Output Enable
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
VCC = +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
21
A0–A20
DQ0–DQ7
8
CE#
OE#
WE#
RESET#
RY/BY#
21444B-7
6 Am29F016B

6 Page









Am29F016B-120DPC1 pdf, datenblatt
PRELIMINARY
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary
Sector Group Unprotect
Completed (Note 2)
Notes:
21444B-8
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group Unprotect
Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= VIL, CE# = VIH or WE# = VIH. To initiate a write cy-
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to reading array data on
power-up.
12 Am29F016B

12 Page





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