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PDF Am29DL800BB120EC Data sheet ( Hoja de datos )

Número de pieza Am29DL800BB120EC
Descripción 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only/ Simultaneous Operation Flash Memory
Fabricantes Advanced Micro Devices 
Logotipo Advanced Micro Devices Logotipo



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No Preview Available ! Am29DL800BB120EC Hoja de datos, Descripción, Manual

PRELIMINARY
Am29DL800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
s Simultaneous Read/Write operations
— Host system can program or erase in one bank,
then immediately and simultaneously read from
the other bank
— Zero latency between read and write operations
— Read-while-erase
— Read-while-program
s Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
s Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29DL800 device
s High performance
— Access times as fast as 70 ns
s Low current consumption (typical values
at 5 MHz)
— 7 mA active read current
— 21 mA active read-while-program or read-while-
erase current
— 17 mA active program-while-erase-suspended
current
— 200 nA in standby mode
— 200 nA in automatic sleep mode
— Standard tCE chip enable access time applies to
transition from automatic sleep mode to active
mode
s Flexible sector architecture
— Two 16 Kword, two 8 Kword, four 4 Kword, and
fourteen 32 Kword sectors in word mode
— Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and
fourteen 64 Kbyte sectors in byte mode
— Any combination of sectors can be erased
— Supports full chip erase
s Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
s Sector protection
— Hardware method of locking a sector to prevent
any program or erase operation within that
sector
— Sectors can be locked in-system or via
programming equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s Top or bottom boot block configurations
available
s Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases sectors or entire chip
— Embedded Program algorithm automatically
programs and verifies data at specified address
s Minimum 1,000,000 program/erase cycles
guaranteed per sector
s Package options
— 44-pin SO
— 48-pin TSOP
— 48-ball FBGA
s Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
— Superior inadvertent write protection
s Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
s Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or
erase cycle completion
s Erase Suspend/Erase Resume
— Suspends or resumes erasing sectors to allow
reading and programming in other sectors
— No need to suspend if sector is in the other bank
s Hardware reset pin (RESET#)
— Hardware method of resetting the device to
reading array data
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 21519 Rev: A Amendment/+3
Issue Date: April 1998

1 page




Am29DL800BB120EC pdf
CONNECTION DIAGRAMS
PRELIMINARY
RY/BY# 1
A18 2
A17 3
A7 4
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
CE# 12
VSS 13
OE# 14
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
SO
44 RESET#
43 WE#
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
32 VSS
31 DQ15/A-1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
FBGA
Bump Side (Bottom) View
A1 B1 C1
A3 A4 A2
A2 B2 C2
A7 A17 A6
A3
RY/BY#
B3
NC
C3
A18
A4 B4
WE# RESET#
C4
NC
A5 B5 C5
A9 A8 A10
A6 B6 C6
A13 A12 A14
D1 E1 F1 G1 H1
A1
A0
CE#
OE#
VSS
D2 E2 F2 G2 H2
A5
DQ0 DQ8
DQ9 DQ1
D3 E3 F3 G3 H3
NC DQ2 DQ10 DQ11 DQ3
D4 E4 F4 G4 H4
NC DQ5 DQ12 VCC DQ4
D5 E5 F5 G5 H5
A11 DQ7 DQ14 DQ13 DQ6
D6 E6 F6 G6 H6
A15 A16 BYTE# DQ15/A-1 VSS
21519A-3
Special Handling Instructions for FBGA
Package
Special handling is required for Flash Memory products
in FBGA packages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be
compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of
time.
Am29DL800B
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Am29DL800BB120EC arduino
PRELIMINARY
Table 2. Am29DL800BT Top Boot Sector Architecture
Bank
Sector
Sector Address
Bank Address
A18 A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
(x8)
Address Range
SA0 0 0 0 0 X X X
64/32
00000h–0FFFFh
SA1 0 0 0 1 X X X
64/32
10000h–1FFFFh
SA2 0 0 1 0 X X X
64/32
20000h–2FFFFh
SA3 0 0 1 1 X X X
64/32
30000h–3FFFFh
SA4 0 1 0 0 X X X
64/32
40000h–4FFFFh
SA5 0 1 0 1 X X X
64/32
50000h–5FFFFh
SA6 0 1 1 0 X X X
Bank 2
SA7 0 1 1 1 X X X
64/32
64/32
60000h–6FFFFh
70000h–7FFFFh
SA8 1 0 0 0 X X X
64/32
80000h–8FFFFh
SA9 1 0 0 1 X X X
64/32
90000h–9FFFFh
SA10 1 0 1 0 X X X
64/32
A0000h–AFFFFh
SA11 1 0 1 1 X X X
64/32
B0000h–BFFFFh
SA12 1 1 0 0 X X X
64/32
C0000h–CFFFFh
SA13 1 1 0 1 X X X
64/32
D0000h–DFFFFh
SA14 1 1 1 0 0 0 X
16/8
E0000h–E3FFFh
01X
SA15 1 1 1 0
10X
32/16
E4000h–E7FFFh,
E8000h–EBFFFh
SA16 1 1 1 0 1 1 0 8/4 EC000h–EDFFFh
SA17 1 1 1 0 1 1 1 8/4 EE000h–EFFFFh
Bank 1
SA18 1 1 1 1 0 0 0 8/4 F0000h–F1FFFh
SA19 1 1 1 1 0 0 1 8/4 F2000h–F3FFFh
01X
SA20 1 1 1 1
10X
32/16
F4000h–F7FFFh,
F8000h–FBFFFh
SA21 1 1 1 1 1 1 X
16/8
FC000h–FFFFFh
(x16)
Address Range
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–71FFFh
72000h–73FFFh
74000h–75FFFh
76000h–76FFFh
77000h–77FFFh
78000h–78FFFh
79000h–79FFFh
7A000h–7BFFFh
7C000h–7DFFFh
7E000h–7FFFFh
Note: The address range is A18:A-1 if in byte mode (BYTE# = VIL). The address range is A18:A0 if in word mode (BYTE# = VIH).
Am29DL800B
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