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PDF BS62LV4005SI Data sheet ( Hoja de datos )
| Número de pieza | BS62LV4005SI | |
| Descripción | Low Power/Voltage CMOS SRAM 512K X 8 bit | |
| Fabricantes | Brilliance Semiconductor | |
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BSI Low Power/Voltage CMOS SRAM
512K X 8 bit
BS62LV4005
FEATURES
GENERAL DESCRIPTION
• Vcc operation voltage : 4.5V ~ 5.5V
• Low power consumption
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I -grade: 50mA (Max.) operating current
1.5uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 5.0V
-55 55ns (Max.) at Vcc = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
Vcc
TEMPERATURE RANGE
BS62LV4005SC
BS62LV4005EC
BS62LV4005TC
+0 O C to +70O C
BS62LV4005STC
BS62LV4005PC
BS62LV4005SI
BS62LV4005EI
BS62LV4005TI
-40O C to +85O C
BS62LV4005STI
BS62LV4005PI
PIN CONFIGURATIONS
4.5V ~ 5.5V
4.5V ~ 5.5V
The BS62LV4005 is a high performance, low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with maximum access time of 55/ 70ns
in 5V operation.
Easy memory expansion is provided by active LOW chip
enable (CE), active LOW output enable (OE) and three-state
output drivers.
The BS62LV4005 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4005 is available in the JEDEC standard 32 pin SOP
, TSOP, TSOP II and STSOP .
SPEED
( ns )
Vcc = 5.0V
POWER DISSIPATION
STANDBY
( ICCSB1 , Max )
Operating
( ICC, Max )
Vcc = 5.0V
Vcc=5.0V
55 / 70
15uA
45mA
55 / 70
25uA
50mA
FUNCTIONAL BLOCK DIAGRAM
PKG TYPE
SOP-32
TSOP2-32
TSOP-32
STSOP-32
PDIP-32
SOP-32
TSOP2-32
TSOP-32
STSOP-32
PDIP-32
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 BS62LV4005SC 25
9 BS62LV4005SI
10
11
BS62LV4005EC
BS62LV4005EI
BS62LV4005PC
24
23
22
12 BS62LV4005PI 21
13 20
14 19
15 18
16 17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV4005TC
BS62LV4005STC
BS62LV4005TI
BS62LV4005STI
32 OE
31 A10
30 CE
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 GND
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE
WE
OE
Vdd
Gnd
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 X 2048
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
2048
8 Column I/O
Write Driver
Sense Amp
8
256
Column Decoder
16
Address Input Buffer
A11 A9 A8 A3 A2 A1 A0 A10
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV4005
1
Revision 2.4
April 2002
1 page  
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
READ CYCLE2 (1,3,4)
t OH
t AA
t RC
CE
D OUT
READ CYCLE3 (1,4)
ADDRESS
OE
CE
D OUT
t ACS
t (5)
CLZ
t RC
t AA
t OE
t OLZ
t ACS
t (5)
CLZ
BS62LV4005
t OH
t (5)
CHZ
t OH
t OHZ (5)
t (1,5)
CHZ
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV4005
5
Revision 2.4
April 2002
5 Page 
BSI
BS62LV4005
REVISION HISTORY
Revision
2.2
2.3
2.4
Description
2001 Data Sheet release
Date
Note
Apr. 15, 2001
Modify Standby Current (Typ. and Jun. 29, 2001
Max.)
Modify some AC parameters.
April,10,2002
R0201-BS62LV4005
11
Revision 2.4
April 2002
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet BS62LV4005SI.PDF ] | |
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