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Teilenummer | N682387 |
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Beschreibung | Dual Programmable Extended Codec/SLCC + SLFC | |
Hersteller | nuvoton | |
Logo | ||
Gesamt 30 Seiten N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
1. DESCRIPTION
The N682386/87, implements a dual channel FXS telephone line interface optimized for short loop applications. It
integrates SLCC (Subscriber Line Control Circuit) functionality with a dual programmable CODEC and a dual DC/DC
controller. The SLCC supports internal ringing up to 90 VPK (5 REN at 4k ft) ideal for Customer Premise Equipment
(CPE). The CODEC can be configured for μ-law, A-law or 16-bit linear PCM encoding. It also supports a
comprehensive set of signaling capabilities required to supervise and control the telephone lines. These include tone
generation, ring tones, DTMF detection/ generation as well as FSK generation. An on-chip Pulse Width Modulation
(PWM) driver allows control of an inductor based DC/DC converter. Programmable impedance and trans-hybrid
balancing allow for worldwide deployment.
2. FEATURES
¡ Complete BORSCHT functions
¡ Internal balanced and unbalanced ringing up to 90
VPK (5 REN up to 4k ft)
¡ Integrated Power Management Options
Integrated DC/DC controller regulates battery
voltage to minimize power dissipation in all
operating modes
Programmable external battery switching
¡ Programmable linefeed characteristics
Ringing Frequency, Amplitude, and Cadence
Trapezoidal and Sinusoidal waveforms
Two wire AC impedance, and trans-hybrid
balance
Constant Current feed (20 to 41) mA
Ring Trip and Loop Closure Thresholds
Ground Key Detection
¡ Programmable signal generation and detection
DTMF generation/ detection and Tone
generation
Frequency Shift Keying (FSK) Enhanced Caller
ID generation (Type I and Type II)
¡ Loop test and diagnostics support
Integrated loopback modes
Real-time linefeed monitoring
On-chip temperature sensor
Line Card Diagnostics Support
¡ Digital interfaces
PCM: G.711 μ-Law, A-Law and 16-bit linear
GCI and SPI bus
Programmable audio path gains
¡ Both PCM Master and Slave modes supported
¡ On-chip PLL for flexible clocking options including
1.0 MHz and 2.0 MHz BCLK operation
¡ Operating voltage: 3.3V
¡ Narrowband Codec (N682386)
¡ Wideband and Narrowband codec (N682387)
¡ Optional integrated (N681622) or discrete
Subscriber Line Feed Circuit
APPLICATIONS
¡ Residential VoIP Gateways / Routers/ IP-PBX
¡ Fiber to the Premise/Home (FTTP/H)
¡ Wireless Local Loop
¡ Optical Network Terminals (ONT)
¡ Analog Telephone Adapter (ATA)
¡ Voice enabled DSL/Cable Modems
¡ Integrated Access Devices
¡ Set Top Boxes
Ordering Information
Part Number
N682386MG
N682387MG
N682386YG
N682387YG
Temp
Range (oC)
-40 to 85
-40 to 85
Package
64-TQFP
64-QFN..
Package
Material
Pb-Free
Pb-Free
N681622YG -40 to 85
U.S. Patent # 7260212 B1
20-QFN
Pb-Free
! WARNING !
HIGH VOLTAGE WARNING USE EXTREME CAUTION
High voltage sources could cause serious injury or
death if not used in accordance with design and/or user
specifications, if they are used by untrained or
unqualified personnel. Before testing Nuvoton’s products
read and understand all instructions, and safety
procedures as in industry standard safe practices.
Revision 1.3
Page 1 of 160
Sep 2010
5. BLOCK DIAGRAM
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Figure 3: Block Diagram
Revision 1.3
Page 6 of 160
Sep 2010
6 Page N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.12.3. TIP, RING, AND LOOP CURRENT (READ ONLY) ................................................................................123
14.12.4. POLARITY..............................................................................................................................................123
14.12.5. COMMON MODE VOLTAGE .................................................................................................................124
14.12.6. TIP EMITTER VOLTAGE FOR TRANSISTORS QT1 SENSE (READ ONLY) .......................................124
14.12.7. TIP VOLTAGE FOR TRANSISTOR QT1 SENSE (READ ONLY) ..........................................................124
14.12.8. RING EMITTER VOLTAGE FOR TRANSISTOR QT1 SENSE (READ ONLY) ......................................125
14.12.9. RING VOLTAGE FOR TRANSISTOR QT1 SENSE (READ ONLY) .......................................................125
14.12.10. TEMPERATURE SENSE (READ ONLY) ...............................................................................................125
14.12.11. BAND GAP VOLTAGES.........................................................................................................................125
14.12.12. PEAK TO PEAK LOOP VOLTAGE.........................................................................................................126
14.12.13. PEAK TO PEAK LOOP CURRENT (READ ONLY) ................................................................................126
14.13. POWER ALARM LPF POLE REGISTERS.............................................................................................127
14.13.1. POWER ALARM COUNTER (READ ONLY)..........................................................................................127
14.13.2. POWER ALARM LOW PASS FILTER POLE FOR TRANSISTORS 1/2/3 ............................................127
14.13.3. POWER ALARM THRESHOLD FOR TRANSISTOR 1-3.......................................................................128
14.14.
IMPEDANCE MATCHING 1/2 ................................................................................................................128
14.14.1. TEMPERATURE ALARM THRESHOLD ................................................................................................129
14.14.2. LOOP CLOSURE MASK COUNT ..........................................................................................................129
14.14.3. COARSE CALIBRATION INTERNAL RESISTOR .................................................................................129
14.14.4. OSCILLATOR 2 RINGING PHASE DELAY............................................................................................129
14.15.
CALIBRATION .......................................................................................................................................130
14.16.
DC OFFSET REGISTERS .....................................................................................................................131
14.16.1. DC OFFSET (RING, TIP, AND VBAT) ...................................................................................................131
14.16.2. PWM COUNT .........................................................................................................................................131
14.17.
TONE GENERATION REGISTERS .......................................................................................................132
14.17.1. OSCILLATOR CONTROL ......................................................................................................................132
14.17.2. RING CONTROL ....................................................................................................................................132
14.17.3. OSCILLATOR 1 AND 2 INITIAL CONDITION LOW/HIGH .....................................................................132
14.17.4. OSCILLATOR 1 AND 2 COEFFICIENT LOW/HIGH ..............................................................................133
14.18. OSCILLATOR 1 AND 2 ACTIVE/ INACTIVE TIME LOW/HIGH .............................................................133
14.19.
GENERAL TONE GENERATION...........................................................................................................134
14.19.1. RING OFFSET .......................................................................................................................................134
14.19.2. ADC/DAC DIGITAL GAIN.......................................................................................................................134
14.19.3. PWM DC/DC FINE TUNING ..................................................................................................................135
14.19.4. PWM DC/DC FINE TUNING SKIP PERIOD...........................................................................................135
14.19.5. PWM DC/DC FINE TUNING ..................................................................................................................136
14.19.6. IMPEDANCE MATCH REGISTER .........................................................................................................137
14.19.6.1. IMPEDENCE MATCHING COEFFICIENT RAM ....................................................................................137
Revision 1.3
Page 12 of 160
Sep 2010
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ N682387 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
N682386 | Dual Programmable Extended Codec/SLCC + SLFC | nuvoton |
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