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N32901U2DN Schematic ( PDF Datasheet ) - nuvoton

Teilenummer N32901U2DN
Beschreibung ARM926-based Media Processor
Hersteller nuvoton
Logo nuvoton Logo 




Gesamt 30 Seiten
N32901U2DN Datasheet, Funktion
N3290x
Data Sheet
ARM926-based Media Processor
Nuvoton Technology Corp.
http://www.nuvoton.com/
1 Release Date: May. 2013
Rev. A5.1






N32901U2DN Datasheet, Funktion
N3290X DATASHEET
2. FEATURES
CPU
ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache & 8KB D-Cache
Frequency up to [email protected] core power operation voltage
JTAG interface supported for development and debugging
Internal SRAM & ROM
8KB internal SRAM and 16KB IBR internal booting ROM supported
IBR booting messages displayed by UART console for debugging supported
Different system booting modes supported:
Memory card
SD card
SD-to-NAND flash bridge
Raw NAND Flash
SPI Flash
USB
EDMA (Enhanced DMA)
Totally 5 DMA channels supported
4 peripheral DMA channels for transfer between memory and on-chip peripherals,
such as ADC, UART and SPI
One dedicated channel for memory-to-memory transfer
Byte, half-word and word data width types supported
Single and burst transfer modes supported
Block transfer supported in memory-to-memory transfer channel
Color format transformation supported in memory-to-memory transfer channel
Source color format could be RGB555, RGB565 and YCbCr422
Destination color format could be RGB555, RGB565 and YCbCr422
Auto reload supported for continuous data transfer
Interrupt generation supported in the half-of-transfer or end-of-transfer
Capture (CMOS Sensor I/F)
CCIR601 & CCIR656 interfaces supported for connection to CMOS image sensor
Resolution up to 2M pixel for Still Image Capture, 640x480 (VGA) resolution for MJPEG
Video Streaming
YUV422 and RGB565 color format supported for data-in from CMOS sensor
YUV422, RGB565, RGB555 and Y-only color format supported for data storing to system
memory
Planar and packet data formats supported for data storing to system memory
Image cropping supported with the cropping window up to 4096x2048
Image scaling-down supported
Vertical and horizontal scaling-down for preview mode supported
The scaling factor is N/M
Two pairs of configurable 8-bit N and 8-bit M for vertical and horizontal scaling-
down
The value of N has to equal to or less than M
Frame rate control supported
Combines two interlace fields to a single frame supported for data in from TV-decoder
JPEG Codec
Baseline Sequential mode JPEG codec function compliant with ISO/IEC 10918-1
Nuvoton Technology Corp.
http://www.nuvoton.com/
6 Release Date: May. 2013
Rev. A5.1

6 Page









N32901U2DN pdf, datenblatt
3. PIN DIAGRAM
3.1 N32901U1DN (LQFP-128)
N3290X DATASHEET
GPB[1] / SDDAT1[0] / UHL_DM1 /
GPB[0] / SDDAT1[1] / UHL_DP1 /
GPB[14] / LMVSYNC /
GPB[13] /WDT_RST_ /
SPCLK
SCLKO
ISDA
ISCK
GPD[12] / SPI0_CLK
GPD[13] / SPI0_CS0_
GPD[14] / SPI0_DI
GPD[15] / SPI0_DO
GPE[4] / SDDAT[2]
GPE[5] / SDDAT[3]
GPE[6] /
SDCMD
GPE[7] /
SDCLK
GPE[2] / SDDAT[0]
GPE[3] / SDDAT[1]
XIN
XOUT
VDD18
MVSSQ
MVDDQ
MVSSQ
MVDDQ
MVDD
MVREF
UD_VDD18
UD_VSS
UD_DM
UD_DP
UD_VDD33
UD_REXT
MVDD
VSS
GPE[1] / SVSYNC / LVDATA[17]
1
10
20
30
MVSSQ
AADDAACC__HHPPOVDU_TD_3L3
ADAC_HPVSS33
MVDDQ
MVDDQ
90 MVSSQ
MVREF
MVSS
VDD18
UD_CDET
TRST_ / HUR_RTS / SPI0_CS1_/ GPD[4]
TDO / HUR_CTS / PWM3
/ GPD[3]
TDI / HUR_RXD / PWM2
/ GPD[2]
TMS / HUR_TXD / PWM1
/ GPD[1]
TCK / SPI1_CS1_/ PWM0
/ GPD[0]
80 RST_
GPA[0]
GPA[1] / SD_CD_
GPA[2] / LMVSYNC
GPA[3] / UHL_DP1
GPA[4] / UHL_DM1
GPA[5] / SPI0_CS1_
GPA[6] / SPI1_CS1_
VDD33
RTC_VDD
70 RTC_RPWR
RTC_RWAKE_
RTC_XIN
RTC_XOUT
ADC_AIN[3]
MVSS
Nuvoton Technology Corp.
http://www.nuvoton.com/
12 Release Date: May. 2013
Rev. A5.1

12 Page





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