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W77C032A Schematic ( PDF Datasheet ) - nuvoton

Teilenummer W77C032A
Beschreibung 8-BIT MICROCONTROLLER
Hersteller nuvoton
Logo nuvoton Logo 




Gesamt 30 Seiten
W77C032A Datasheet, Funktion
W77C32/W77C032A Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION .......................................................................................................... 3
2. FEATURES.................................................................................................................................. 3
3. PIN CONFIGURATIONS ............................................................................................................. 4
4. PIN DESCRIPTION ..................................................................................................................... 5
5. FUNCTIONAL DESCRIPTION .................................................................................................... 6
6. MEMORY ORGANIZATION ........................................................................................................ 8
6.1 Program Memory............................................................................................................. 8
6.2 Data Memory ................................................................................................................... 8
7. SPECIAL FUNCTION REGISTERS .......................................................................................... 10
7.1 External Interrupt Flag ................................................................................................... 16
7.2 Timer 2 Mode Control.................................................................................................... 23
7.2.1
Timer 2 Capture LSB ..............................................................................................24
8. INSTRUCTION .......................................................................................................................... 27
8.1 Instruction Timing .......................................................................................................... 34
8.2 MOVX Instruction .......................................................................................................... 36
8.3 External Data Memory Access Timing .......................................................................... 38
8.4 Wait State Control Signal .............................................................................................. 40
9. POWER MANAGEMENT .......................................................................................................... 42
9.1 Idle Mode....................................................................................................................... 42
9.2 Economy Mode.............................................................................................................. 42
9.3 Power Down Mode ........................................................................................................ 43
10. RESET CONDITIONS ............................................................................................................... 45
10.1 External Reset ............................................................................................................... 45
10.2 Watchdog Timer Reset ................................................................................................. 45
10.3 Reset State.................................................................................................................... 45
11. INTERRUPTS............................................................................................................................ 47
11.1 Interrupt Sources ........................................................................................................... 47
11.2 Priority Level Structure .................................................................................................. 48
11.3 Interrupt Response Time............................................................................................... 49
12. PROGRAMMABLE TIMERS/COUNTERS ................................................................................ 51
12.1
Timer/Counters 0 & 1 .................................................................................................... 51
12.1.1
Time-base Selection ...............................................................................................51
12.1.2
Mode 0 ....................................................................................................................52
Publication Release Date: February 1, 2007
- 1 - Revision A8






W77C032A Datasheet, Funktion
W77C32/W77C032A
5. FUNCTIONAL DESCRIPTION
The W77C032 is 8052 pin compatible and instruction set compatible. It includes the resources of the
standard 8052 such as four 8-bit I/O Ports, three 16-bit timer/counters, full duplex serial port and
interrupt sources.
The W77C032 features a faster running and better performance 8-bit CPU with a redesigned core
processor without wasted clock and memory cycles. it improves the performance not just by running at
high frequency but also by reducing the machine cycle duration from the standard 8052 period of
twelve clocks to four clock cycles for the majority of instructions. This improves performance by an
average of 1.5 to 3 times. The W77C032 also provides dual Data Pointers (DPTRs) to speed up block
data memory transfers. It can also adjust the duration of the MOVX instruction (access to off-chip data
memory) between two machine cycles and nine machine cycles. This flexibility allows the W77C032 to
work efficiently with both fast and slow RAMs and peripheral devices. In addition, the W77C032
contains on-chip 1KB MOVX SRAM, the address of which is between 0000H and 03FFH. It only can be
accessed by MOVX instruction; this on-chip SRAM is optional under software control.
The W77C032 is an 8052 compatible device that gives the user the features of the original 8052
device, but with improved speed and power consumption characteristics. It has the same instruction set
as the 8051 family, with one addition: DEC DPTR (op-code A5H, the DPTR is decreased by 1). While
the original 8051 family was designed to operate at 12 clock periods per machine cycle, the W77C032
operates at a much reduced clock rate of only 4 clock periods per machine cycle. This naturally speeds
up the execution of instructions. Consequently, the W77C032 can run at a higher speed as compared
to the original 8052, even if the same crystal is used. Since the W77C032 is a fully static CMOS design,
it can also be operated at a lower crystal clock, giving the same throughput in terms of instruction
execution, yet reducing the power consumption.
The 4 clocks per machine cycle feature in the W77C032 is responsible for a three-fold increase in
execution speed. The W77C032 has all the standard features of the 8052, and has a few extra
peripherals and features as well.
I/O Ports
The W77C032 has four 8-bit ports and one extra 4-bit port. Port 0 can be used as an Address/Data bus
when external program is running or external memory/device is accessed by MOVC or MOVX
instruction. In these cases, it has strong pull-ups and pull-downs, and does not need any external pull-
ups. Otherwise it can be used as a general I/O port with open-drain circuit. Port 2 is used chiefly as the
upper 8-bits of the Address bus when port 0 is used as an address/data bus. It also has strong pull-ups
and pull-downs when it serves as an address bus. Port 1 and 3 act as I/O ports with alternate functions.
Port 4 is only available on 44-pin PLCC/QFP package type. It serves as a general purpose I/O port as
Port 1 and Port 3. The P4.0 has an alternate function WAIT which is the wait state control signal.
When wait state control signal is enabled, P4.0 is input only.
Serial I/O
The W77C032 has two enhanced serial ports that are functionally similar to the serial port of the
original 8052 family. However the serial ports on the W77C032 can operate in different modes in order
to obtain timing similarity as well. Note that the serial port 0 can use Timer 1 or 2 as baud rate
generator, but the serial port 1 can only use Timer 1 as baud rate generator. The serial ports have
the enhanced features of Automatic Address recognition and Frame Error detection.
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W77C032A pdf, datenblatt
W77C32/W77C032A
Data Pointer Select
Bit: 7 6 5 4 3 2 1 0
- - - - - - - DPS.0
Mnemonic: DPS
Address: 86h
DPS.0: This bit is used to select either the DPL, DPH pair or the DPL1, DPH1 pair as the active Data
Pointer. When set to 1, DPL1, DPH1 will be selected, otherwise DPL, DPH will be selected.
DPS.1-7: These bits are reserved, but will read 0.
Power Control
Bit: 7
6
SM0D SMOD0
5
-
43210
- GF1 GF0 PD IDL
Mnemonic: PCON
Address: 87h
SMOD: This bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1.
SMOD0: Framing Error Detection Enable: When SMOD0 is set to 1, then SCON.7(SCON1.7) indicates
a Frame Error and acts as the FE(FE_1) flag. When SMOD0 is 0, then SCON.7(SCON1.7)
acts as per the standard 8052 function.
GF1-0: These two bits are general purpose user flags.
PD: Setting this bit causes the W77C032 to go into the POWER DOWN mode. In this mode all the
clocks are stopped and program execution is frozen.
IDL: Setting this bit causes the W77C032 to go into the IDLE mode. In this mode the clocks to the
CPU are stopped, so program execution is frozen. But the clock to the serial, timer and
interrupt blocks is not stopped, and these blocks continue operating.
Timer Control
Bit: 7
6
TF1 TR1
Mnemonic: TCON
54
TF0 TR0
321
IE1 IT IE0
Address: 88h
0
IT
TF1: Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when
the program does a timer 1 interrupt service routine. Software can also set or clear this bit.
TR1: Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.
TF0: Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when
the program does a timer 0 interrupt service routine. Software can also set or clear this bit.
TR0: Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off.
IE1: Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1. This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
IT1: Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
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