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M0564LE4AE Schematic ( PDF Datasheet ) - nuvoton

Teilenummer M0564LE4AE
Beschreibung 32-BIT MICROCONTROLLER
Hersteller nuvoton
Logo nuvoton Logo 




Gesamt 30 Seiten
M0564LE4AE Datasheet, Funktion
M0564
ARM CORTEX® -M
32-BIT MICROCONTROLLER
NuMicro® Family
M0564 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
May 05, 2017
Page 1 of 161
Rev 1.00






M0564LE4AE Datasheet, Funktion
M0564
LIST OF FIGURES
Figure 4.2-1 NuMicro® M0564 Base Series LQFP 48-pin Diagram ............................................... 23
Figure 4.2-2 NuMicro® M0564 Base Series LQFP 64-pin Diagram ............................................... 24
Figure 4.2-3 NuMicro® M0564 Base Series LQFP 100-pin Diagram ............................................. 25
Figure 5.1-1 NuMicro® M0564 Block Diagram ............................................................................... 55
Figure 6.1-1 Functional Block Diagram.......................................................................................... 56
Figure 6.2-1 System Reset Sources .............................................................................................. 59
Figure 6.2-2 nRESET Reset Waveform ......................................................................................... 61
Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 62
Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 63
Figure 6.2-5 Brown-out Detector (BOD) Waveform ....................................................................... 64
Figure 6.2-6 NuMicro® M0564 Power Mode State Machine .......................................................... 66
Figure 6.2-7 NuMicro® M0564 Power Distribution Diagram........................................................... 69
Figure 6.2-8 SRAM Block Diagram ................................................................................................ 72
Figure 6.2-9 SRAM Memory Organization ..................................................................................... 73
Figure 6.2-10 UART1_TXD Modulated with PWM Channel .......................................................... 74
Figure 6.2-11 VDET Block Diagram............................................................................................... 75
Figure 6.3-1 Clock Generator Block Diagram ................................................................................ 82
Figure 6.3-2 Clock Generator Global View Diagram...................................................................... 83
Figure 6.3-3 System Clock Block Diagram .................................................................................... 84
Figure 6.3-4 HXT Stop Protect Procedure ..................................................................................... 85
Figure 6.3-5 SysTick Clock Control Block Diagram ....................................................................... 85
Figure 6.3-6 Clock Source of Clock Output ................................................................................... 86
Figure 6.3-7 Clock Output Block Diagram ..................................................................................... 87
Figure 6.10-1 Hardware Divider Block Diagram ............................................................................ 94
Figure 6.16-22 SPI Timing in Master Mode ................................................................................. 102
Figure 6.16-23 SPI Timing in Master Mode (Alternate Phase of SPIx_CLK) .............................. 102
Figure 6.16-24 SPI Timing in Slave Mode ................................................................................... 103
Figure 6.16-25 SPI Timing in Slave Mode (Alternate Phase of SPIx_CLK) ................................ 103
Figure 6.17-13 PWM Prescale Waveform in Up Count Type ...................................................... 108
Figure 6.17-14 PWM Up Count Type........................................................................................... 108
Figure 6.17-15 PWM Down Count Type ...................................................................................... 109
Figure 6.17-16 PWM Up-Down Count Type ................................................................................ 110
Figure 6.17-17 PWM Comparator Events in Up-Down Count Type ............................................ 111
Figure 6.17-18 Period Loading Mode with Up Count Type.......................................................... 112
Figure 6.17-19 Immediately Loading Mode with Up Count Type................................................. 113
Figure 6.17-20 PWM Pulse Generation in Up-Down Count Type ............................................... 113
May 05, 2017
Page 6 of 161
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M0564LE4AE pdf, datenblatt
M0564
Built-in 22.1184 MHz high speed RC oscillator for system operation (Frequency
variation < 2% at -40oC ~ +105oC)
Built-in 48 MHz internal high speed RC oscillator (Frequency variation < 2% at -40oC ~
+105oC)
Built-in 10 kHz low speed RC oscillator for Watchdog Timer and Wake-up operation
Built-in 4~24 MHz high speed crystal oscillator for precise timing operation
Built-in 32.768 kHz low speed crystal oscillator for Real Time Clock
Supports PLL up to 144 MHz for high resolution PWM operation
Supports dynamically calibrating the HIRC48 to 48 MHz ±0.25% by external 32.768K
crystal oscillator (LXT)
Supports dynamically calibrating the HIRC to 22.1184Mhz by external 32.768K crystal
oscillator (LXT)
Supports clock on-the-fly switch
Supports clock failure detection for system clock
Supports auto clock switch once clock failure detected
Supports exception (NMI) generated once a clock failure detected
Supports divided clock output
GPIO
Four I/O modes
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level trigger setting
Supports high driver and high sink current I/O (up to 20 mA at 5V)
Supports software selectable slew rate control
Supports up to 81/49/35 GPIOs for LQFP100/64/48 respectively
Timer/PW M
Supports 4 sets of Timers/PWM
Timer Mode
PWM Mode
TM_CNT_OUT
PWM_CH0
TM_EXT
PWM_CH1 (Complementary)
Timer Mode
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale
counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Supports event counting function to count the event from external pin
Supports input capture function to capture or reset counter value
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to
trigger PWM, EADC and PDMA function
Supports Inter-Timer trigger mode
PWM Mode
Supports maximum clock frequency up to 50MHz
Supports independent mode for 4 sets of independent PWM output channel
Supports complementary mode for 4 sets of complementary paired PWM output
channel with 12-bit Dead-time generator
Supports 12-bit pre-scalar from 1 to 4096
May 05, 2017
Page 12 of 161
Rev 1.00

12 Page





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