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Teilenummer | MPC970 |
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Beschreibung | LOW VOLTAGE PLL CLOCK DRIVER | |
Hersteller | Motorola Semiconductors | |
Logo | ||
Gesamt 16 Seiten MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Not Recommended for New Designs
See MPC972 or MPC974
Low Voltage PLL Clock Driver
MPC970
The MPC970 is a 3.3V compatible, PLL based clock driver devices
targeted for high performance RISC or CISC processor based systems.
• Fully Integrated PLL
• Output Frequency Up to 250MHz
• Compatible with PowerPC™ and Pentium™ Processors
• Output Frequency Configuration
• On–Board Crystal Oscillator
• 52–Lead TQFP Packaging
• ±50ps Typical Cycle–to–Cycle Jitter
LOW VOLTAGE
PLL CLOCK DRIVER
The MPC970 was designed specifically to drive today’s PowerPC 601
and Pentium processors while providing the necessary performance to
address higher frequency PowerPC 601 as well as PowerPC 603 and
PowerPC 604 applications. The 2x_PCLK output can toggle at up to
250MHz while the remaining outputs can be configured to drive the other
system clocks for MPC 601 based systems. As the processor based
clock speeds increase the processor bus will likely run at one third or
even one fourth the processor clock. The MPC970 supports the
necessary waveforms to drive the BCLKEN input signal of the MPC 601
when the processor bus is running at a lower frequency than the
FA SUFFIX
52–LEAD TQFP PACKAGE
CASE 848D–03
processor. The MPC970 uses an advanced PLL design which minimizes
the jitter generated on the outputs. The jitter specification is well within the
requirements of the Pentium processor and meets the stringent
preliminary specifications of the PowerPC 603 and PowerPC 604
processors. The application section of this data sheet deals in more detail
with driving PowerPC and Pentium processor based systems.
The external feedback option of the MPC970 provides for a near zero delay between the reference clock input and the outputs
of the device. This feature is required in applications where a master clock is being picked up off the backplane and regenerated
and distributed on a daughter card. The advanced PLL of the MPC970 eliminates the dead zone of the phase detector and
minimizes the jitter of the PLL so that the phase error variation is held to a minimum. This phase error uncertainty makes up a
major portion of the part–to–part skew of the device.
For single clock driver applications the MPC970 provides an internal oscillator and internal feedback to simplify board layout
and minimize system cost. By using the on–board crystal oscillator the MPC970 acts as both the clock generator and distribution
chip. The external component is a relatively inexpensive crystal rather than a more expensive oscillator. Since in single board
applications the delay between the input reference and the outputs is inconsequential an internal feedback option is offered. The
internal feedback simplifies board design in that the system designer need not worry about noise being coupled into the feedback
line due to board parasitics and layout. The internal feedback is a fixed divide by 32 of the VCO. This divide ratio ensures that the
input crystals will be ≤20MHz, thus keeping the crystal costs down and ensuring availability from multiple vendors.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
1/97
© Motorola, Inc. 1997
1
REV 2
MPC970
AC CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
Min Typ Max Unit
Condition
fXtal
Fout
tDC
VOHAC
VOLAC
tpw
tper
fVCO
tjitter
Crystal Oscillator Frequency
Maximum 2x_PCLK Output Frequency
Output Duty Cycle (Notes 4., 5.)
AC Output HIGH Voltage
AC Output LOW Voltage
2x_PCLK Pulse Width (Notes 4., 5.)
Minimum Clock Out Period
VCO Lock Range
Output Jitter (Notes 4., 5.)
10 25 MHz Note 3.
200 MHz Note 4.
45 55 % Fout < 200MHz
35 65 Fout ≥ 200MHz
2.4 V Fout < 200MHz
2.2 Fout ≥ 200MHz
0.4 V Fout < 200MHz
0.6 Fout ≥ 200MHz
1.75 2.27
ns Fout = 200MHz
4.85 4.91
ns Fout = 200MHz
200 700 MHz
±50
±100
ps PLL Jitter
110 190
2x_P Period Variation
76 210
Period Variation (Other)
tskew
Output–to–Output Skew (Notes 4., 5.)
2x_PCLCK, PCLKEN, BCLKEN, BCLK
2x_PCLK, PCLKEN, BCLK
PCI_CLK
BCLK
All
ps
550 MPC601_Clks = ‘0’
550 MPC601_Clks = ‘1’
450
550
800
tdelay
tr, tf
tlock
tPZL
tPHZ, tPLZ
fMAX
ts
Propagation Delay
2x_PCLK to BCLKEN
Output Rise/Fall Time (Notes 4., 5.)
PLL Lock Time
Output Enable Time MR/Tristate to Outputs
Output Disable Time MR/Tristate to Outputs
Maximum Frz_Clk Frequency
Setup Time
Frz_Data to Frz_Clk
Com_Frz to Frz_Strobe
100
0.15
8
5
850 ps MPC601_Clks = ‘1’
1.5 ns 0.8 to 2.0V
10 ms
8 ns
10 ns
20 MHz
th Hold Time
Frz_Clk to Frz_Data
Frz_Strobe to Com_Frz
3. See Applications Info section for more crystal information.
4. Drive 50Ω transmission lines.
5. Measured at 1.4V.
8
5
MOTOROLA
6 TIMING SOLUTIONS
BR1333 — Rev 6
6 Page MPC970
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC970 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 9 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC970 clock
driver is effectively doubled due to its capability to drive
multiple lines.
MPC970
OUTPUT
BUFFER
IN 7Ω
RS = 43Ω ZO = 50Ω
OutA
MPC970
OUTPUT
BUFFER
IN 7Ω
RS = 43Ω ZO = 50Ω
RS = 43Ω ZO = 50Ω
OutB0
OutB1
Figure 9. Single versus Dual Transmission Lines
The waveform plots of Figure 10 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC970 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC970. The output waveform
in Figure 10 shows a step in the waveform, this step is
caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 43Ω series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 11 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
3.0
OutA
2.5 tD = 3.8956
2.0
In
1.5
OutB
tD = 3.9386
1.0
0.5
0
2 4 6 8 10 12 14
TIME (nS)
Figure 10. Single versus Dual Waveforms
MPC970
OUTPUT
BUFFER
7Ω
RS = 36Ω ZO = 50Ω
RS = 36Ω ZO = 50Ω
7Ω + 36Ω k 36Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 11. Optimized Dual Line Termination
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
Using the Output Freeze Circuitry
With the recent advent of a “green” classification for
computers the desire for unique power management among
system designers is keen. The individual output enable
control of the MPC970 allows designers, under software
control, to implement unique power management schemes
into their designs. Although useful, individual output control
at the expense of one pin per output is too high, therefore a
simple serial interface was derived to economize on the
control pins.
The freeze control logic provides two mechanisms through
which the MPC970 clock outputs may be frozen (stopped in
the logic ‘0’ state):
The first freeze mechanism allows serial loading of the
13–bit Serial Input Register, this register contains one
programmable freeze enable bit for 13 of the 15 output
clocks. The BCLK0 and PCI_CLK0 outputs cannot be frozen
with the serial port, this avoids any potential lock up situation
MOTOROLA
12 TIMING SOLUTIONS
BR1333 — Rev 6
12 Page | ||
Seiten | Gesamt 16 Seiten | |
PDF Download | [ MPC970 Schematic.PDF ] |
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