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MPC9773 Schematic ( PDF Datasheet ) - Freescale Semiconductor

Teilenummer MPC9773
Beschreibung 3.3 V 1:12 LVCMOS PLL Clock Generator
Hersteller Freescale Semiconductor
Logo Freescale Semiconductor Logo 




Gesamt 19 Seiten
MPC9773 Datasheet, Funktion
Freescale Semiconductor
Technical Data
MPC9773
Rev 5, 08/2005
3.3 V 1:12 LVCMOS PLL Clock
Generator
MPC9773
The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted
for high-performance low-skew clock distribution in mid-range to high-
performance networking, computing, and telecom applications. With output
frequencies up to 240 MHz and output skews less than 250 ps the device meets
the needs of the most demanding clock applications.
Features
• 1:12 PLL based low-voltage clock generator
• 3.3 V power supply
• Internal power-on reset
• Generates clock signals up to 242.5 MHz
• Maximum output skew of 250 ps
• Differential PECL reference clock input
• Two LVCMOS PLL reference clock inputs
• External PLL feedback supports zero-delay capability
• Various feedback and output dividers (refer to Application Section)
• Supports up to three individual generated output clock frequencies
• Synchronous output clock stop circuitry for each individual output for power
down support
• Drives up to 24 clock lines
• Ambient temperature range -40°C to +85°C
• Pin and function compatible to the MPC973
• 52-lead Pb-free package available
3.3 V 1:12 LVCMOS
PLL CLOCK GENERATOR
FA SUFFIX
52-LEAD LQFP PACKAGE
CASE 848D-03
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 848D-03
Functional Description
The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs as
well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-
tion, the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-
binary factor. The MPC9773 also supports the 180° phase shift of one of its output banks with respect to the other output banks.
The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system
baseline timing signals.
The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative
LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass con-
figuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers,
bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics
do not apply.
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
MPC9773. The MPC9773 has an internal power-on reset.
The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission
lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.
© Freescale Semiconductor, Inc., 2005. All rights reserved.






MPC9773 Datasheet, Funktion
Table 10. AC Characteristics (VCC = 3.3 V ± 5%, TA = -40°C to 85°C)(1), (2)
Symbol
Characteristics
Min
fREF Input Reference Frequency
÷ 4 feedback
÷ 6 feedback
÷ 8 feedback
÷ 10 feedback
÷ 12 feedback
÷ 16 feedback
÷ 20 feedback
÷ 24 feedback
÷ 32 feedback
÷ 40 feedback
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
6.25
5.00
Typ
Max
121.2
80.8
60.6
48.5
40.4
30.3
24.2
20.2
15.1
12.1
Unit Condition
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
PLL bypass
Input Reference Frequency in PLL Bypass Mode
250 MHz
fVCO
fMAX
VCO Frequency Range
Output Frequency
÷ 2 output
÷ 4 output
÷ 6 output
÷ 8 output
÷ 10 output
÷ 12 output
÷ 16 output
÷ 20 output
÷ 24 output
200
100.0
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
485
242.5
121.2
80.8
60.6
48.5
40.4
30.3
24.2
20.2
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
fSTOP_CLK Serial Interface Clock Frequency
20 MHz
VPP
VCMR
tPW,MIN
tR, tF
t()
tSK(O)
Peak-to-Peak Input Voltage
PCLK, PCLK
Common Mode Range(3)
PCLK, PCLK
Input Reference Pulse Width(4)
CCLKx Input Rise/Fall Time(5)
Propagation Delay (static phase offset)(6)
6.25 MHz < fREF < 65.0 MHz
65.0 MHz < fREF < 125 MHz
fREF = 50 MHz and feedback = ÷8
Output-to-Output Skew(7)
within QA outputs
within QB outputs
within QC outputs
all outputs
400
1.2
2.0
–3
–4
–166
1000
VCC – 0.9
1.0
+3
+4
+166
100
100
100
250
mV LVPECL
V LVPECL
ns
ns 0.8 to 2.0 V
PLL locked
°
°
ps
ps
ps
ps
ps
DC Output Duty Cycle(8)
(T÷2) –200 T÷2 (T÷2) +200 ps
tR, tF
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT()
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle Jitter(9)
Period Jitter(10)
I/O Phase Jitter RMS (1 σ)(11)
0.1
÷ 4 feedback
÷ 6 feedback
÷ 8 feedback
÷ 10 feedback
÷ 12 feedback
÷ 16 feedback
÷ 20 feedback
÷ 24 feedback
÷ 32 feedback
÷ 40 feedback
1.0 ns 0.55 to 2.4 V
8.0 ns
8.0 ns
150 ps
100 ps
11 ps (VCO = 400 MHz)
86 ps
13 ps
88 ps
16 ps
19 ps
21 ps
22 ps
27 ps
30 ps
MPC9773
6
Advanced Clock Drivers Device Data
Freescale Semiconductor

6 Page









MPC9773 pdf, datenblatt
Due to the statistical nature of I/O jitter, an RMS value (1
σ) is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 12.
Table 12. Confidence Factor CF
CF
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
Probability of Clock Edge
within the Distribution
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device.
Due to the frequency dependence of the static phase
offset and I/O jitter, using Figure 9 to Figure 11 to predict a
maximum I/O jitter and the specified t() parameter relative to
the input reference frequency results in a precise timing
performance analysis.
In the following example calculation an I/O jitter confidence
factor of 99.7% (± 3σ) is assumed, resulting in a worst-case
timing uncertainty from the common input reference clock to
any output of –455 ps to +455 ps relative to CCLK (PLL
feedback = ÷8, reference frequency = 50 MHz, VCO
frequency = 400 MHz, I/O jitter = 13 ps RMS max., static
phase offset t() = ± 166 ps):
tSK(PP) = [–166ps...166ps] + [–250ps...250ps] +
[(13ps –3)...(13ps 3)] + tPD, LINE(FB)
tSK(PP) = [–455ps...455ps] + tPD, LINE(FB)
Maximum I/O Phase Jitter versus Frequency Parameter:
PLL Feedback Divider FB
160
140
120
100
80
60
40
20
0
200
FB = ÷32
FB = ÷16
FB = ÷8
FB =÷4
250
300 350 400
VCO frequency [MHz]
450 480
Figure 9. MPC9773 I/O Jitter
Maximum I/O Phase Jitter versus Frequency Parameter:
PLL Feedback Divider FB
120
100
80 FB = ÷6
60 FB = ÷24
40
20 FB = ÷12
0
200 250 300 350 400
VCO frequency [MHz]
Figure 10. MPC9773 I/O Jitter
450 480
Maximum I/O Phase Jitter versus Frequency Parameter:
PLL Feedback Divider FB
140
120
100
80
60
40
20
0
200
FB = ÷10
FB = ÷40
FB = ÷20
250 300 350 400
VCO frequency [MHz]
Figure 11. MPC9773 I/O Jitter
450 480
Driving Transmission Lines
The MPC9773 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω, the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale Semiconductor
application note AN1091. In most high-performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme, either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50-resistance to VCC ÷ 2.
MPC9773
12
Advanced Clock Drivers Device Data
Freescale Semiconductor

12 Page





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