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L93C66 Schematic ( PDF Datasheet ) - LIZE

Teilenummer L93C66
Beschreibung EEPROM
Hersteller LIZE
Logo LIZE Logo 




Gesamt 11 Seiten
L93C66 Datasheet, Funktion
Shenzhen LIZE Electronic Technology Co., Ltd
SPECIFICATION
L 3C56/66
Version 1.0
reserves the right to change this documentation without prior notice.






L93C66 Datasheet, Funktion
Tel:86-755-8835 3502/03/04
Website:http://www.lizhiic.com
Fax:86-755-8835 3509
Functional Description
The L93C56/66 is accessed via a simple and versatile three-wire serial communication interface. Device operation is
controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and
consists of a start bit (logic“1”) followed by the appropriate op code and the desired memory address location.
Table5.Instruction Set for the L93C56/66
Instruction SB OP Code
Address
x8 x16
Data
x8 x16
Comments
READ 1
10
A8 - A0
A7 - A0
Reads data stored in memory, at specified address
EWEN 1
00 11XXXXXXX 11XXXXXX
Write enable must precede all programming modes
ERASE 1
11
A8 - A0
A7 - A0
Erase memory location An - A0
WRITE 1
01
A8 - A0
A7 - A0
D7 - D0 D15 - D0
Writes memory location An - A0
ERAL 1
00 10XXXXXXX 10XXXXXX
Erases all memory locations. Valid only at VCC = 4.5V to 5.5V
WRAL 1
00 01XXXXXXX 01XXXXXX D7 - D0 D15 - D0 Writes all memory locations. Valid only at VCC = 4.5V to 5.5V
EWDS 1
00 00XXXXXXX 00XXXXXX
Disables all programming instructions
Notes: The X’s in the address field represent don’t care values and must be clocked.
READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the
instruction and address are decoded, data from the selected memory location is available at the serial output pin DO.
Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit
(logic “0”) precedes the 8- or 16-bit data output string.The K93C56/66 supports sequential read operations.The device
will automatically increment the internal address pointer and clock out the next memory location as long as Chip Select
(CS) is held high .In this case ,the dummy bit (logic “0”)will not be clocked out between memory locations,thus allowing
for a continuous steam of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS)
state when power is first applied. An Erase/Write Enable(EWEN) instruction must be executed first before any
programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1”
state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (TCS). A logic “1” at
pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified
memory location. The self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input
pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (TCS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory
location at the specified address has been written with the data pattern contained in the instruction and the part is
ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the
selftimed programming cycle, TWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state
and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high
after being kept low for a minimum of 250 ns (TCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
Shenzhen LIZE Electronic Technology Co., Ltd
Version: 1.0
Date: 22, Dec. 2008
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