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MPC972 Schematic ( PDF Datasheet ) - Motorola Semiconductors

Teilenummer MPC972
Beschreibung LOW VOLTAGE PLL CLOCK DRIVER
Hersteller Motorola Semiconductors
Logo Motorola Semiconductors Logo 




Gesamt 16 Seiten
MPC972 Datasheet, Funktion
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC972/D
Rev 6, 09/2001
Low Voltage PLL Clock Driver
The MPC972 is a 3.3 V compatible, PLL based clock driver device
targeted for high performance CISC or RISC processor based systems.
With output frequencies of up to 125 MHz and skews of 550 ps the MPC972
is ideally suited for most synchronous systems. The device offers twelve low
skew outputs plus a feedback and sync output for added flexibility and ease
of system implementation.
MPC972
Fully Integrated PLL
Output Frequency up to 125 MHz
Compatible with PowerPCand PentiumMicroprocessors
LQFP Packaging
3.3 V VCC
LOW VOLTAGE
PLL CLOCK DRIVER
• ± 100 ps Typical Cycle–to–Cycle Jitter
The MPC972 features an extensive level of frequency programmability
between the 12 outputs as well as the input vs output relationships. Using
the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2,
5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock
edge prior to the coincident edges of the Qa and Qc outputs. The Sync
output will indicate when the coincident rising edges of the above
relationships will occur. The selectability of the feedback frequency is
independent of the output frequencies, this allows for very flexible
programming of the input reference vs output frequency relationship. The
output frequencies can be either odd or even multiples of the input
reference. In addition the output frequency can be less than the input
SCALE 2:1
frequency for applications where a frequency needs to be reduced by a
non–binary factor. The Power–On Reset ensures proper programming if the
FA SUFFIX
frequency select pins are set at power up. If the fselFB2 pin is held high, it
may be necessary to apply a reset after power–up to ensure
52–LEAD LQFP PACKAGE
CASE 848D-03
synchronization between the QFB output and the other outputs. The internal
power–on reset is designed to provide this function, but with power–up
conditions being dependent, it is difficult to guarantee. All other conditions of
the fsel pins will automatically synchronize during PLL lock acquisition.
The MPC972 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system debug as
well as provide unique opportunities for system power down schemes to meet the requirements of “green” class machines. The
MPC972 allows for the enabling of each output independently via a serial input port. When disabled or “frozen” the outputs will be
locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen” the outputs will
activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of outputs occurs only
when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A power-on reset will ensure
that upon power up all of the outputs will be active. Note that all of the control inputs on the MPC972 have internal pull–up resistors.
The MPC972 is fully 3.3 V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL
compatible levels while the outputs provide LVCMOS levels with the capability to drive 50 transmission lines. For series
terminated lines each MPC972 output can drive two 50 lines in parallel thus effectively doubling the fanout of the device.
The MPC972 can consume significant power in some configurations. Users are encouraged to review Application Note
AN1545/D in the Advanced Clock Drivers Device Data book (DL207/D) for a discussion on the thermal issues with the MPC family
of clock drivers.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
Motorola, Inc. 2001
t






MPC972 Datasheet, Funktion
MPC972
AC CHARACTERISTICS (TA = 0° to 70°C; VCC = 3.3V ±5%)
Symbol
Characteristic
Min Typ Max Unit
Condition
tr, tf Output Rise/Fall Time
tpw Output Duty Cycle
0.15
tCYCLE/2
750
tCYCLE/2
±500
1.2
tCYCLE/2
+750
ns 0.8 to 2.0V, Note 6.
ps Note 6.
tpd SYNC to Feedback
Propagation Delay
TCLK0
TCLK1
270
330
130
70
530 ps Notes 6., 7.; QFB = ÷8
470
tos
fVCO
fmax
Output-to-Output Skew
VCO Lock Range
Maximum Output Frequency
Q (÷2)
Q (÷4)
Q (÷6)
Q (÷8)
200
550 ps Note 6.
480 MHz
125 MHz Note 6.
120
80
60
tjitter CycletoCycle Jitter (PeaktoPeak)
±100
ps Note 6.
tPLZ, tPHZ
Output Disable Time
2 8 ns Note 6.
tPZL, tPZH
Output ENable TIme
2 10 ns Note 6.
tlock Maximum PLL Lock Time
10 ms
fMAX
Maximum Frz_Clk Frequency
20 MHz
6. 50transmission line terminated into VCC/2.
7. tpd is specified for a 50MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/longer input reference
periods. The tpd does not include jitter.
APPLICATIONS INFORMATION
Programming the MPC972
The MPC972 is one of the most flexible frequency
programming devices in the Motorola timing solution portfolio.
With three independent banks of four outputs as well as an
independent PLL feedback output the total number of possible
configurations is too numerous to tabulate. Table 1 tabulates
the various selection possibilities for the three banks of outputs.
The divide numbers presented in the table represent the divider
applied to the output of the VCO for that bank of outputs. To
determine the relationship between the three banks the three
divide ratios would be compared. For instance if a frequency
relationship of 5:3:2 was desired the following selection could
be made. The Qb outputs could be set to ÷10, the Qa outputs
to ÷6 and the Qc outputs to ÷4. With this output divide selection
the desired 5:3:2 relationship would be generated. For
situations where the VCO will run at relatively low frequencies
the PLL may not be stable for the desired divide ratios. For
these circumstances the VCO_Sel pin allows for an extra ÷2 to
be added into the clock path. When asserted this pin will
maintain the desired output relationships, but will provide an
enhanced lock range for the PLL. Once the output frequency
relationship is set and the VCO is in its stable range the
feedback output would be programmed to match the input
reference frequency.
The MPC972 offers only an external feedback to the PLL. A
separate feedback output is provided to optimize the flexibility
of the device. If in the example above the input reference
frequency was equal to the lowest output frequency the
feedback output would be set in the ÷10 mode. If the input
needed to be half the lowest frequency output the fselFB2 input
could be asserted to halve the feedback frequency. This action
multiplies the output frequencies by two relative to the input
reference frequency. With 7 unique feedback divide capabilities
there is a tremendous amount of flexibility. Again assume the
above 5:3:2 relationship is needed with the highest frequency
output equal to 100 MHz. If one was also constrained because
the only reference frequency available was 50 MHz the setup
in Figure 6 could be used. The MPC972 provides the 100, 66
and 40 MHz outputs all synthesized from the 50 MHz source.
With its multitude of divide ratio capabilities the MPC972 can
generate almost any frequency from a standard, common
frequency already present in a design. Figure 7 and Figure 8
illustrate a few more examples of possible MPC972
configurations.
The MPC972 has one more programming feature added to
its arsenal. The Inv_Clk input pin when asserted will invert the
Qc2 and Qc3 outputs. This inversion will not affect the
outputoutput skew of the device. This inversion allows for the
development of 180° phase shifted clocks. This output could
also be used as a feedback output to the MPC972 or a second
PLL device to generate early or late clocks for a specific design.
Figure 9 illustrates the use of two MPC972s to generate two
banks of clocks with one bank divided by 2 and delayed by 180°
relative to the first.
6 MOTOROLA

6 Page









MPC972 pdf, datenblatt
MPC972
4X
0.20 (0.008) H L-M N
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 848D03
ISSUE D
4X 13 TIPS
0.20 (0.008) T L-M N
CL
AB
X
X=L, M, N
G
52
1
L
40
39
3X VIEW Y
M
BV
13
14
A1
S1
N
27
26
A
S
B1 V1
H
T
SEATING
PLANE
C
4X q2
4X q3
0.10 (0.004) T
VIEW AA
0.05 (0.002) S
C2
C1
VIEW AA
W
q1
q
K
E
Z
2X R R1
0.25 (0.010)
GAGE PLANE
AB
VIEW Y
PLATING F BASE METAL
JÉÉÉÉÇÇÉÉÇÇÉÉÇÇ U
D
0.13 (0.005) M T L-M S N S
SECTION ABAB
ROTATED 90_ CLOCKWISE
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4 DATUMS -L-, -M- AND -N- TO BE DETERMINED
AT DATUM PLANE -H-.
5 DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -T-.
6 DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE ĆHĆ.
7 DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 10.00 BSC
0.394 BSC
A1 5.00 BSC
0.197 BSC
B 10.00 BSC
0.394 BSC
B1 5.00 BSC
0.197 BSC
C --- 1.70 --- 0.067
C1 0.05 0.20 0.002 0.008
C2 1.30 1.50 0.051 0.059
D 0.20 0.40 0.008 0.016
E 0.45 0.75 0.018 0.030
F 0.22 0.35 0.009 0.014
G 0.65 BSC
0.026 BSC
J 0.07 0.20 0.003 0.008
K 0.50 REF
0.020 REF
R1 0.08 0.20 0.003 0.008
S 12.00 BSC
0.472 BSC
S1 6.00 BSC
0.236 BSC
U 0.09 0.16 0.004 0.006
V 12.00 BSC
0.472 BSC
V1 6.00 BSC
0.236 BSC
W 0.20 REF
0.008 REF
Z 1.00 REF
0.039 REF
θ 0_ 7_
θ1 0_ ---
θ2 12_ REF
θ3 12_ REF
0_ 7_
0_ ---
12_ REF
12_ REF
12 MOTOROLA

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