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PDF DS0128 Data sheet ( Hoja de datos )

Número de pieza DS0128
Descripción IGLOO2 FPGA and SmartFusion2 SoC FPGA
Fabricantes Microsemi　
Logotipo Microsemi Logotipo



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DS0128
Datasheet
IGLOO2 FPGA and SmartFusion2 SoC FPGA

1 page




DS0128 pdf
Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
IGLOO2 and SmartFusion2 Design Security Densities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
IGLOO2 and SmartFusion2 Data Security Densities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
FPGA Operating Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Embedded Operating Flash Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device Storage Temperature and Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
High Temperature Data Retention (HTR) Lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package Thermal Resistance of SmartFusion2 and IGLOO2 Devices . . . . . . . . . . . . . . . . . . . . . 10
Quiescent Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SmartFusion2 and IGLOO2 Quiescent Supply Current (VDD = 1.2 V) – Typical Process . . . . . . . 12
Currents During Program Cycle, 0 °C < = TJ <= 85 °C – Typical Process . . . . . . . . . . . . . . . . . . . 13
Currents During Verify Cycle, 0 °C <= TJ <= 85 °C – Typical Process . . . . . . . . . . . . . . . . . . . . . . 13
SmartFusion2 and IGLOO2 Quiescent Supply Current (VDD = 1.26 V) – Worst-Case Process . . 13
Average Junction Temperature and Voltage Derating Factors for Fabric Timing Delays . . . . . . . . 14
Inrush Currents at Power up, –40 °C <= TJ <= 100 °C – Typical Process . . . . . . . . . . . . . . . . . . . 14
Timing Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum Data Rate Summary Table for Single-Ended I/O in Worst-Case Industrial Conditions . 19
Maximum Data Rate Summary Table for Voltage-Referenced I/O in Worst-Case
Industrial Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Maximum Data Rate Summary Table for Differential I/O in Worst-Case Industrial Conditions . . . 20
Maximum Frequency Summary Table for Single-Ended I/O in Worst-Case Industrial Conditions . 20
Maximum Frequency Summary Table for Voltage-Referenced I/O in Worst-Case Industrial
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum Frequency Summary Table for Differential I/O in Worst-Case Industrial Conditions . . . 21
Input Capacitance, Leakage Current, and Ramp Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I/O Weak Pull-up/Pull-down Resistances for DDRIO I/O Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I/O Weak Pull-Up/Pull-Down Resistances for MSIO I/O Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
I/O Weak Pull-up/Pull-down Resistances for MSIOD I/O Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Schmitt Trigger Input Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LVTTL/LVCMOS 3.3 V DC Recommended DC Operating Conditions (Applicable to MSIO I/O
Bank Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LVTTL/LVCMOS 3.3 V Input Voltage Specification (Applicable to MSIO I/O Bank Only) . . . . . . . 24
LVCMOS 3.3 V DC Output Voltage Specification (Applicable to MSIO I/O Bank Only) . . . . . . . . . 24
LVTTL 3.3 V DC Output Voltage Specification (Applicable to MSIO I/O Bank Only) . . . . . . . . . . . 24
LVTTL/LVCMOS 3.3 V AC Maximum Switching Speed (Applicable to MSIO I/O Bank Only) . . . . 24
LVTTL/LVCMOS 3.3 V Receiver Characteristics for MSIO I/O Bank (Input Buffers) . . . . . . . . . . . 25
LVTTL/LVCMOS 3.3 V Transmitter Characteristics for MSIO I/O Bank (Output and
Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications (Applicable to MSIO I/O Bank Only) . . 25
LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications for MSIO I/O Bank . . . . . . . . . . 25
LVCMOS 2.5 V DC Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVCMOS 2.5 V DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVCMOS 2.5 V DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVCMOS 2.5 V AC Minimum and Maximum Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVCMOS 2.5 V AC Calibrated Impedance Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVCMOS 2.5 V Receiver Characteristics (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LVCMOS 2.5 V Transmitter Characteristics for DDRIO Bank (Output and Tristate Buffers) . . . . . 27
LVCMOS 2.5 V AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LVCMOS 2.5 V Transmitter Drive Strength Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LVCMOS 2.5 V Transmitter Characteristics for MSIO Bank (Output and Tristate Buffers) . . . . . . 28
LVCMOS 1.8 V DC Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LVCMOS 1.8 V DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LVCMOS 1.8 V DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DS0128 Datasheet Revision 11.0
v

5 Page





DS0128 arduino
Revision History
1 Revision History
1.1
1.2
1.3
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
Revision 11.0
The following is a summary of the changes in revision 11.0 of this document.
• Updated Table 24, page 22 with minimum and maximum values for input current low and high (SAR
73114 and 80314).
• Added Non-Deterministic Random Bit Generator (NRBG) Characteristics, page 106 (SAR 73114
and 79517).
• Added 060 device in Table 282, page 110 (SAR 79860).
• Added DEVRST_N to Functional Times, page 116 (SAR 73114).
• Added Cryptographic Block Characteristics, page 106 (SAR 73114 and 79516).
• Update Table 296, page 121 with VTX-AMP details (SAR 81756).
• Update note in Table 297, page 122 (SAR 74570 and 80677).
• Update Table 298, page 122 with generic EPCS details (SAR 75307).
• Added Table 308, page 129 (SAR 50424).
Revision 10.0
The following is a summary of the changes in revision 10.0 of this document.
• The Surge Current on VDD during DEVRST_B Assertion and Surge Current on VDD during Digest
Check using System Services tables were deleted and added reference to AC393: Board Design
Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Application Note. (SAR 76865 and 76623).
• Added 060 device in Table 4, page 6 (SAR 76383).
• Updated Table 24, page 22 for ramp time input (SAR 72103).
• Added 060 device details in Table 284, page 112 (SAR 74927).
• Updated Table 290, page 116 for name change (SAR 74925).
• Updated Table 283, page 111 for 060 FG676 Package details (SAR 78849).
• Updated Table 305, page 126 for SmartFusion2 and Table 310, page 129 for IGLOO2 for SPI timing
and Fmax (SAR 56645, 75331).
• Updated Table 293, page 119 for Flash*Freeze entry and exit times (SAR 75329, 75330).
• Updated Table 297, page 122 for RX-CID information (SAR 78271).
• Added Table 8, page 8 and Figure 1, page 9 (SAR 78932).
• Updated Table 223, page 76 for timing characteristics and Table 224, page 77(SAR 75998).
• Added SRAM PUF, page 105 (SAR 64406).
• Added a footnote on digest cycle in Table 5, page 7 (SAR 79812).
Revision 9.0
The following is a summary of the changes in revision 9.0 of this document.
• Added a note in Table 5, page 7 (SAR 71506).
• Added a note in Table 6, page 8 (SAR 74616).
• Added a note in Figure 3, page 17 (SAR 71506).
• Updated Quiescent Supply Current for 060 in Table 11, page 12 and Table 12, page 13 (SAR
74483).
• Updated programming currents for 060 in Table 13, page 13, Table 14, page 13, and Table 15,
page 14.
• Added DEVRST_B assertion tables (SAR 74708).
• Updated I/O speeds for LVDS 3.3 V in Table 18, page 19 and Table 21, page 20 (SAR 69829).
• Updated Table 24, page 22 (SAR 69418).
• Updated Table 25, page 22, Table 26, page 23, Table 27, page 23 (SAR 74570).
• Updated all AC/DC table to link to the Input Capacitance, Leakage Current, and Ramp Time,
page 22 for reference (SAR 69418).
DS0128 Datasheet Revision 11.0
1

11 Page







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