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uP1561 Schematic ( PDF Datasheet ) - uPI Semiconductor

Teilenummer uP1561
Beschreibung Synchronous Buck Controller
Hersteller uPI Semiconductor
Logo uPI Semiconductor Logo 




Gesamt 17 Seiten
uP1561 Datasheet, Funktion
Conceptual
uP1561
Synchronous Buck Controller with 3A VTT LDO
for Memory Power Solution
General Description
Features
The uP1561 is a high performance synchronous buck
controller with 3A source/sink VTT LDO for memory
systems power. It also provides the buffered low noise
reference. The uP1561 has wide operation ranging from
3.0V to 26V for input power and 0.75V~3.0V for memory
output voltage.
The synchronous buck of the uP1561 adopts constant-
on-time PWM scheme that features easy-to-use, low
external component count, fast transient response and
quasi- constant frequency operation over the operation
range or in current mode to support ceramic output
capacitors.
The 3A source/sink VTT LDO has fast transient response,
requiring only two 10uF of ceramic output capacitors. In
addition, the LDO supply input is available externally to
significantly reduce the total power losses. The uP1561
supports all the sleep state controls, in S3 state (suspend
to RAM) VTT is at high-Z and in S4/S5 (suspend to disk)
VDDQ, VTT and VTTREF soft off.
The uP1561 has complete functions including under
voltage protection, over current protection, over voltage
protection, power-up sequencing, power OK output, and
thermal shutdown. The uP1561 is available in VQFN4x4-
24L and WQFN3x3-20L packages.
Applications
Desktop PCs, Notebooks, and Workstations
Microprocessor and Chipset Supplies
DDR3/DDR2 Memory Power Supplies
SSTL-2 SSTL-18 and HSTL Bus Termination
Synchronous Buck Controller (VDDQ)
Wide Input Voltage Range 3.0V to 26V
Fast Load Transient Response
Current Mode Option Supports Ceramic
Output Capacitors
Soft-Off in S4/S5 States
R Current Sensing Technique
DS(ON)
1.5V (DDR3), 1.8V (DDR2) Fixed Output or
Adjustable Output (0.75V to 3.0V)
POK, OVP, and UVP
3A LDO (VTT)
3A Source/Sink Capability
Two 10uF Ceramic Output Capacitors
Support High Z in S3 and Soft-Off in S4/S5
Thermal Shutdown
+20mV Accuracy
Reference Voltage (VTTREF)
+20mV Accuracy
Low Noise +10mA Output
Ordering Information
Order Number Package Type
Remark
uP1561PQAG VQFN4x4-24L
uP1561QQKF WQFN3x3-20L
Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 requirement. They are halogen-free,
RoHS compliant and 100% matte tin (Sn) plating that are
suitable for use in SnPb or Pb-free soldering processes.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. C00, File Name: uP1561-DS-C0000
1






uP1561 Datasheet, Funktion
Conceptual
uP1561
Functional Description
The uP1561 is a high performance synchronous buck
controller with 3A source/sink VTT LDO for memory
systems power. It also provides the buffered low noise
reference with 10mA capability.
The buck controller adopts constant-on-time PWM
scheme that features easy-to-use, low external component
count, fast transient response and quasi-constant
frequency operation over the operation range or in current
mode to support ceramic output capacitors.
The 3A source/sink VTT LDO has fast transient response
that only requires two 10uF of ceramic output capacitors.
The reference voltage tracks VDDQ/2 within 1% of VDDQ.
The VTT tracks VTTREF within 20mV at no load condition
and within 40mV over all load conditions.
The uP1561 supports all the sleep state controls, and also
has complete functions including over current protection,
over voltage protection, thermal shutdown, power-up
sequencing, power OK output, and thermal shutdown. The
uP1561 is available in space-saving VQFN4X4-24L and
WQFN3x3-20L package.
Soft Start and POK
The soft start function of the uP1561 SMPS is achieved
by two-stage current clamp and ramping up reference as
shown in Figure 1. It takes about 40us for the V to ramp
DDQ
up after S5 is set high.
At the first stage, the reference voltage is set as 87% of
nominal level (650mV) and the current clamp level is set
as 1/2 of nominal level. The output voltage ramping-up
slew rate is decided by the current clamp level and the
output capacitors.
When the uP1561 detects VDDQ becoming greater than
80% of its target value, the second stage begins and the
reference voltage ramps up raised toward 750mV. The
output voltage ramping-up slew rate is decided by the
ramping up reference voltage. When the VDDQ is above
95% of its target level, the uP1561 asserts soft start end
and set the current clamp to its nominal level. It takes
about 100us for the V to ramp up from 87% to 95%.
DDQ
The uP1561 turns off the POK open-drain MOS 45us after
the soft start end. Consequently, the total soft start time
(from S5 high to POK high) can be calculated as:
TVDDQSS
=
2 × CVDDQ × VVDDQ
IVDDQLIM
× 0.87
+ 185us
where IVDDQLIM is the current limit value for VDDQ switcher.
Please see the Output Current Limit section for detail
calculation of I
.
VDDQLIM
95%
87%
80%
VDDQ
VOCL
VPOK
VS5 60us
160us 45us
Figure 1. VDDQ Soft Start and POK Timing
The soft-start function of the VTT LDO is achieved by
current limit. The current limit threshold is also changed
in two stages. When VTT is below the internal power OK
threshold, the current limit level is 60% (2.2A). When the
output comes up to the good state to target value, the
current limit level is released to normal value (3.8A). The
POK signal indicates only the status of VDDQ.
Consequently, the total soft start time of VTT LDO can be
calculated as:
TVTTSS
=
CVTT × VVTT
IVTTOCL
where IVTTOCL is 2.2A (typ). In the above calculations, no
load current during start-up are assumed. Note that both
switcher and the LDO do not start up with full load
condition.
Dual Operation Modes VDDQ
The uP1561 synchronous buck supports two control
schemes which would be a current mode and a constant
on time mode. Constant on time mode is used for low
external component count configuration with the
appropriate output capacitor ESR. Current mode control
can be used to achieve stable operation with very low ESR
capacitor such as ceramic capacitors.
Two operation modes are chosen by COMP pin
connection. Connect this pin to VCC5, constant on time
mode is selected, otherwise it works in current mode.
Constant on time control scheme is easy to use due to
simple control logic. At beginning of switching cycle, the
upper MOSFET is turned on at fixed on time which is
determined by VIN and VOUT voltages. The upper MOSFET
is turned off again when IC get insufficient output voltage.
Current mode control is to sense feedback voltage and
inductor current information for output voltage regulation.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. C00, File Name: uP1561-DS-C0000
6

6 Page









uP1561 pdf, datenblatt
Conceptual
uP1561
Electrical Characteristics
Parameter
Symbol
Test Conditions
Internal Bootstrape Diode
Forward Voltage
BOOT Leakage Current
OCP
VFBOOT
IBOOTLK
V ,PVCC5-VBOOT IF = 10mA
VBOOT = 34V, VPHASE = 26V, VVDDQ = 2.6V
Current Limit Threshold
Current Sense Sink Current
Trip Current Temperature Co-
efficient
VOCL
ITRIP
TC
ITRIP
VPGND-CS, POK = High, VCS < 0.5V
VPGND-CS, POK = Low, VCS < 0.5V
VCS > 4.5V, POK = High
VCS> 4.5V, POK = Low
RDS(ON) sense scheme, On the basis of TA =
25OC
Overcurrent Protection
Comparator Offset
VOCL(off)
(V -V
), V = 60mV, V
VCC5-CS PGND-PHASE
VCC5-CS
CS
> 4.5 V
Current Limit Threshold
Setting Range
VR(trip)
VVCC5-CS
POK Comparator
VDDQ POK Threshold
POK in from lower
VTVDDQPOK POK hysteresis
POK Sink Current
IPOK(max) VVTT = 0 V, VPOK = 0.5 V
POK Delay Time
TPOK(del) Delay for POK in
Under Voltage Lockout and Logic Threshold
VCC5 UVLO Threshold
Voltage
VUVVCC5 Wake up
Hysteresis
Mode Threshold
No discharge
VTHMODE Non-tracking discharge
VDDQSET Threshold
Voltage
1.5V output
VTHVDDQSET 1.8V output
High-level Input Voltage
Low-level Input Voltage
Hysteresis Voltage
Logic Input Leakage Current
Input Leakage/ Bias Current
VIH S3, S5
VIL S3, S5
VIHYST S3, S5
VINLEAK S3, S5, MODE
VINVDDQSET VDDQSET
Min Typ Max Unit
0.75 0.85 0.95 V
-- 0.1 1.0 uA
50 60 70 mV
20 30 40 mV
9 10 11 uA
4 5 6 uA
--
4500
--
ppm/-
OC
-9 -4
1 mV
30 -- 300 mV
93 95 97 %
-- 5 -- %
2.5 9.0 -- mA
80 130 200 us
3.7
--
4.7
--
0.15
3.5
2.2
--
--
-1
-1
4.0
0.3
--
--
0.28
4.0
--
--
0.2
--
--
4.3
--
--
0.1
0.35
4.5
--
0.3
--
1
1
V
V
V
V
V
V
V
V
V
uA
uA
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. C00, File Name: uP1561-DS-C0000
12

12 Page





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