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PDF EV12AS200AZP Data sheet ( Hoja de datos )
| Número de pieza | EV12AS200AZP | |
| Descripción | ANALOG TO DIGITAL CONVERTER | |
| Fabricantes | e2v | |
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EV12AS200AZP
ANALOG TO DIGITAL CONVERTER
12‐bit 1.5 GSps
Datasheet
Main features
• Single Core ADC Architecture with 12‐bit Resolution Integrating a Selectable 1:1 and 1:2 DEMUX
• 1.5 GSps Guaranteed Conversion Rate
• 500 mVpp Analog Input Voltage (Differential Full Scale and AC Coupled)
• Very Low Latency (< 5 Clock Cycles)
• Noise Floor of –150 dBm/Hz (13‐bit ENOB in 10 MHz Bandwidth)
• Analog and Clock Input Impedance: 100 Differential
• Power Dissipation: 3.0W (1:1 Mode) ; 3.1W (1:2 Mode)
• Differential Input Clock (AC Coupled)
• LVDS Differential Output Data and Data Ready on the 2 Output Ports
• Write only 3WSI‐like Digital Interface (Gain, Offset, Sampling Delay adjust, DMUX Ratio Selection, test Modes)
• ADC Gain, Offset, Sampling Delay Adjustment for Interleaving Control
• Dynamic Test Mode (Alignment Sequence)
• Power Supplies: VCCA5 = 5.0V, VCCA3 = 3.3V, VCCO = 2.5V or 3.3V
• Package: FpBGA196 15 x15 mm2 196 balls
Performances
• 2.3 GHz Full Power Input Bandwidth (–3 dB)
• Single Tone Performance:
SFDR = –66 dBFS; ENOB = 9.0‐Bit; SNR = 57 dBFS at Fin = 997 MHz @ –1 dBFS, Fs = 1.5 GSps
SFDR = –65 dBFS; ENOB = 8.8‐Bit; SNR = 56 dBFS at Fin = 1600 MHz @ –1 dBFS, Fs = 1.5 GSps
SFDR = –70 dBFS; ENOB = 9.3‐Bit; SNR = 59 dBFS at Fin = 997 MHz @ –12 dBFS, Fs = 1.5 GSps
SFDR = –70 dBFS; ENOB = 9.3‐Bit; SNR = 58.5 dBFS at Fin = 1600 MHz @ –12 dBFS, Fs = 1.5 GSps
• Broadband Performance:
NPR = 48 dB at –14 dBFS Optimum Loading Factor in 1st Nyquist
Applications
• Satellite Communications Systems
• Telecom Test Instrumentation
• Wireless Communications Systems
• Direct RF Down‐conversion
• Automatic Test Equipment
• Direct L‐Band RF Down Conversion
• Radar Systems
• High Resolution Oscilloscopes
e2v semiconductors SAS 2015
Visit our website: www.e2v.com
for the latest version of the datasheet
1122C–BDC–06/15
1 page  
EV12AS200AZP
2.2 Recommended Conditions of Use
Table 2‐2. Recommended Conditions of Use
Parameter
Symbol
Comments
Typ Unit
Power supplies(1)(2)
Differential analog input voltage (Full Scale)
Clock input power level (Ground common mode)
Operating Temperature Range
Storage Temperature
VCC5
VCC3
VCC0
VIN – VINN
PCLK PCLKN
Tcase
Tjunction
Tstg
100 differential
100 differential input
Commercial “C” grade
Industrial “V” grade
5.0
3.3
2.5
500
7
Tc > 0 < Tj < 90
Tc > –40 < Tj < 110
–65 to 150
V
V
V
mVpp
dBm
°C
°C
Note:
1. No specific power supplies sequencing is required; however to benefit from the internal reset at power up, VCC3 should be applied
before VCC5
2. VCCO could be merged to VCC3 to use the device using only 2 power supplies.
2.3 Electrical Characteristics
Unless otherwise stated, values here below are typical values for typical conditions of operation (Troom, typical
power supply).
Table 2‐3. Electrical characteristics
Parameter
ADC RESOLUTION
POWER REQUIREMENTS
Power Supply voltage
- Analogue
- Analogue Core and Digital
- Output buffers (2.5V configuration)
- Output buffers (3V configuration)
Power Supply current in 1:1 DEMUX
- Analogue
- Analogue Core and Digital
- Output buffers
Power Supply current in 1:2 DEMUX Ratio
- Analogue
- Analogue Core and Digital
- Output buffers
Power dissipation DMUX1:1
- 1:1 Ratio with standard LVDS output swing, 750 Msps output
rate (Vcco = 2.5V)
- 1:1 Ratio with standard LVDS output swing, 750 Msps output
rate (Vcco = 3.3V)
Power dissipation DMUX1:2
- 1:2 Ratio with standard LVDS output swing, 1500 Msps output
rate (Vcco = 2.5V)
- 1:2 Ratio with standard LVDS output swing, 1500 Msps output
rate (Vcco = 3.3V)
Symbol
VCC5
VCC3
VCCO
VCCO
I_VCC5
I_VCC3
I_VCCO
I_VCC5
I_VCC3
I_VCCO
PD
PD
PD
PD
Min Typ Max Unit Test Level
12 bit
4.75 5.0 5.25 V 1
3.15 3.3 3.45 V 1
2.4 2.5 2.6 V 1
3.15 3.3 3.45 V 1
170 190 mA 1
535 600 mA 1
50 70 mA 1
170 190 mA 1
540 600 mA 1
90 110 mA 1
2.75 3.0
1
2.9 3.15
4
W
2.85 3.10
1
3.0 3.25
1
e2v semiconductors SAS 2015
1122C–BDC–06/15
5
5 Page 
EV12AS200AZP
Table 2‐4. Dynamic Performance (Continued)
Parameter
IMD3
2Fin1‐ Fin2, 2Fin2‐Fin1, unfilterable
Fin1 = 1450 MHz & Fin2 = 1460 MHz
Amplitude In = –7 dBFs on each tone
IMD3
2Fin1‐ Fin2, 2Fin2‐Fin1, unfilterable
Fin1 = 700 MHz & Fin2 = 710 MHz
Amplitude In = –30 dBFs on each tone
IMD3
2Fin1‐ Fin2, 2Fin2‐Fin1, unfilterable
Fin1 = 1450 MHz & Fin2 = 1460 MHz
Amplitude In = –30 dBFs on each tone
Test
Symbol
Min
Typ
Max Unit Level
IMD3
–65
dBFS
4
IMD3
–82
dBFS
4
IMD3
–81
dBFS
4
2.5 Timing Characteristics and Switching Performances
Unless otherwise stated, values here below are typical values (typical conditions of operations) assuming an
external clock jitter of 75 fs rms.
Table 2‐5. Timing characteristics and Switching Performances
Parameter
SWITCHING PERFORMANCE AND CHARACTERISTICS
Clock frequency (1)
1:1 DEMUX Ratio
1:2 DEMUX Ratio
Symbol
Min
300
300
Typ Max
1000
1500
Test
Unit Level
MHz
Maximum Output Rate per port (Data and Data Ready)
1:1 DEMUX Ratio
1:2 DEMUX Ratio
Maximum Output Frequency per port (Data and Data Ready) (3)
1:1 DEMUX Ratio
1:2 DEMUX Ratio
BER
TIMING
Overvoltage recovery time
ADC step response (10% to 90%)
Overshoot
Ringback
Clock duty cycle
Minimum clock pulse width (high)
Aperture delay (1) (SDA off)
ORT
TC1, TC2
TA
45
300
1000
750
MSps
500
375
10–12
MHz
Error/sample
300 ps 4
120 ps 4
4 %4
–2 % 4
50 55
%4
330 1500 ps 4
50 ps 4
e2v semiconductors SAS 2015
1122C–BDC–06/15
11
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