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65C00 Schematic ( PDF Datasheet ) - Commodore

Teilenummer 65C00
Beschreibung MICROPROCESSORS
Hersteller Commodore
Logo Commodore Logo 




Gesamt 11 Seiten
65C00 Datasheet, Funktion
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MPS
65COO
MICROPROCESSORS
65COO MICROPROCESSORS
THE 65COO MICROPROCESSOR FAMILY CONCEPT -
The 65COO Series Microprocessors represent the first totally software compatible microprocessor
family. This family of products includes a range of software compatible microprocessors which provide a
selection of addressable memory range, Interrupt input options and on-chip clock oscillators and drivers. All of
the microprocessors in the 65COO group are software compatible within the group and are bus compatible with
the M6800 product offering.
The family includes six microprocessors with on-board clock oscillators and drivers and four micropro-
cessors driven by external clocks. The on-chip clock versions are aimed at high performance, low cost
applications where single phase inputs, crystal or RC inputs provide the time base. The external clock versions
are geared for the multi processor system applications where maximum timing control is mandatory. All
versions of the microprocessors are available in 1 MHz maximum operating frequencies.
FEATURES OF THE 6500 FAMILY
• Single +5 volt supply
• Eight bit parallel processing
• 56 Instructions
• Decimal and binary arithmetic
• Thirteen addressing modes
• True indexing capability
• Programmable stack pOinter
• Variable length stack
• Interrupt capability
• Non-maskable interrupt
• Use with any type or speed memory
• 8 BIT Bi-directional Data Bus
• Addressable memory range of up to
65K bytes
• "Ready" input (for single cycle execution)
• Direct memory access capability
• Bus compatible with M6800
• Choice of external or on-board clocks
• 1 MHz operation
• On-the-chip clock options
*External single clock input
*RC time base input
*Crystal time base input
• Pipeline architecture
MEMBERS OF THE 65COO MICROPROCESSOR
(CPU) FAMILY
Microprocessors with On-Chip Clock Oscillator
Model
MPS65C02
MPS65C03
MPS65C04
MPS65C05
MPS65C06
MPS65C07
Addressable Memory
65K Bytes
4K Bytes
8K Bytes
4K Bytes
4K Bytes
8K Bytes
Microprocessors with External Two Phase
Clock Inputs
LMPS65C12
MPS65C13
MPS65C14
MPS65C15
65K Bytes
4K Bytes
8K Bytes
4K Bytes
ORDER NUMBER:
MXS65CXX
~ MODEL DESIGNATOR
xx = 02,03,04, ... 15
PACKAGE DESIGNATOR
=C CERAMIC
P = PLASTIC
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65C00 Datasheet, Funktion
MPS
65COO
I ICOMMON CHARACTERISTICS
65COO SIGNAL DESCRIPTION
Clocks (0" 0,)
The 65C1 X requires a two phase non-overlapping clock that runs at the Vee voltage level.
The 65COX clocks are supplied with an internal clock generator. The frequency of these clocks is extemally controlled.
Address Bus <Ao-A,J
These outputs are TIL compatible, capable of driving one standard TIL load and 130 pf.
Data Bus (Do-~)
Eight pins are used for the data bus. This is a bi-directional bus, transferring data to and from the device and peripherals. The
outputs are tri-state buffers capable of driving one standard TIL load and 13Opf.
Data Bus Enable (DBE)
This TIL compatible input allows external control of the tri-state data output buffers and will enable the microprocessor bus
driver when in the high state. In normal operation DBE would be driven by the phase two (0 2) clock, thus allowing data output
from microprocessor only during O 2, During the read cycle, the data bus drivers are internally disabled, becoming essentially an
open circuit. To disable data bus drivers externally, DBE should be held low.
Ready (ROy)
This input signal allows the user to single cycle the microprocessor on all cycles except write cycles. A negative transition to
the low state during or coincident with phase one (0,) and up to 100ns after phase two (0 2) will halt the microprocessor with the
output address lines reflecting the current address being fetched. This condition will remain through a subsequent phase two
(0 2) in which the Ready signal is low. This feature allows microprocessor interfacing with low speed PROMS as well as fast (max.
2 cycle) Direct Memory Access (DMA). If Ready is low during a write cycle, it is ignored until the following read operation.
Interrupt Request (IRQ)
This TIL level input requests that an interrupt sequence begin within the microprocessor. The microprocessor will complete
the current instruction being executed before recognizing the request. At that time, the interrupt mask bit in the Status Code
Register will be examined. If the interrupt mask flag is not set, the microprocessor will begin an interrupt sequence. The Program
Counter and Processor Status Register are stored in the stack. The microprocessor will then set the interrupt mask flag high so
that no further interrupts may occur. At the end of this cycle, the program counter low will be loaqed from address FFFE, and pro·
gram counter high from location FFFF, therefore transferring program control to the memory vector located at these addresses.
The RDY signal must be in the high state for any interrupno be recognized. A 3KO external resistor should be used for proper
wire-OF~ operation.
Non-Maskable Interrupt (NMI)
A negative going edge on this input requests that a non·maskable interrupt sequence be generated within the microprocessor.
NMI is an unconditional interrupt. Following completion of the current instruction, the sequence of operations defined for IRQ
will be performed, regardless of the interrupt mask flag status. The vector address loaded into the program counter, low and high,
are locations FFFA and FFFB respectively, thereby transferring program control to the memory vector located at these ad-
dresses. The instructions loaded at these locations cause the microprocessor to branch to a non-maskable interrupt routine in
memory.
NMI also requires an external 3KO resister to Vcc for proper wire-OR operations.
Inputs IRQ and NMI are hardware interrupt lines that are sampled during O 2 (phase 2) and will begin the appropriate interrupt
routine on the 0, (phase 1) following the completion of the current instruction.
Set Overflow Flag (5.0.)
A NEGATIVE going edge on this input sets the overflow bit in the Status Code Register. This Signal is sampled on the trailing
edge of 0,.
SYNC
This output line is provided to identify those cycles in which the microprocessor is doing an OP CODE fetch. The SYNC line
goes high during 0, of an OP CODE fetch and stays high for the remainder of that cycle. If the ROY line is pulled low during the
0, clock pulse in which SYNC went high, the processor will stop in its current state and will remain in the state until the ROY line
goes high. In this manner, the SYNC signal can be used to control ROY to cause single instruction execution.
Reset
This input is used to reset or start the microprocessor from a power down condition. During the time that this line is held low,
writing to or from the microprocessor is inhibited. When a positive edge is detected on the input, the microprocessor will im-
mediately begin the reset sequence.
After a system initialization time of six clock cycles, the mask interrupt flag will be set and the microprocessor will load the
program counter from the memory vector locations FFFC and FFFD. This is the start location for program control.
After Vcc reaches 4.75 volts in a power up routine, reset must be held low for at least two clock cycles. At this time the Am and
(SYNC) signal will become valid.
When the reset signal goes high following these two clock cycles, the microprocessor will proceed with the normal reset pro-
cedure detailed above.
I
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