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6530 Schematic ( PDF Datasheet ) - Commodore

Teilenummer 6530
Beschreibung MEMORY / TIMER ARRAY
Hersteller Commodore
Logo Commodore Logo 




Gesamt 11 Seiten
6530 Datasheet, Funktion
,..,commodore
~ semiconductor group
~~@~
MPS
6530
MEMORY,
I/O, TIMER
ARRAY
6530 (MEMORY, I/O, TIMER ARRAY)
DESCRIPTION
The 6530 is designed to operate in conjunction with the 650X Microprocessor Family. It is
comprised of a mask programmable 1024 x8 ROM,a 64x8 static RAM, two software controlled 8bit
bi-directional data ports allowing direct interfacing between the microprocessor unit and peripheral
devices, and a software programmable interval timer with interrupt, capable of timing in various
intervals from 1 to 262,144 clock periods.
FEATURES
• 8 bit bi-directional Data Bus for direct communication with the microprocessor
• 1024 x 8 ROM
• 64 x 8 static RAM
• Two 8 bit bi-directional data ports for interface to peripherals
• Two programmable I/O Peripheral Data Direction Registers
• Programmable Interval Timer
• Programmable Interval Timer Interrupt
• TTL & CMOS compatible peripheral lines
• Peripheral pins with Direct Transistor Drive Capability
• High Impedance Three-State Data Pins
• Allows up to 7K contiguous bytes of ROM with no external decoding
Figure 1. 6530 Block Diagram
DATA
CONTROL
'REGISTER
A
I/O
REGISTER
A
PA7
INTERVAL
TIMER
PERIPHERAL
DATA BUFFER
B
I/O
REGISTER
B
DATA
BUS
BUFFER
DO 01
ADDRESS
DECODER
AO A9
CHIP
SELECT
R/W
64 x 8
RAM
CS1 CS2 ¢2 R/W RES
2-96






6530 Datasheet, Funktion
MPS
6530
INTERNAL ORGANIZATION
A block diagram of the internal architecture is
shown in Figure 1. The 6530 is divided into four basic
sections, RAM, ROM, I/O and TIMER. The RAM and
ROM interface directly with the microprocessorthrough
the system data bus and address lines. The I/O section
consists of 2 8-bit halves. Each half contains a Data
Direction Register (DDR) and an I/O Register.
ROM 1K Byte (8K Bits)
During a read operation the microprocessor is not
reading the I/O Registers but in fact is reading the
peripheral data pins. For the peripheral data pins
which are programmed as outputs the microprocessor
will read the corresponding data bits of the I/O
Register. The only way the I/O Register data can be
changed is by a microprocessor Write operation. The
I/O Register is not affected by a Read of the data on the
peripheral pins.
The 8K ROM is in a 1024 x 8 configuration. Address
lines AO-A9, as well as RSO are needed to address the
entire ROM. With the additio'l of CS1 and CS2, seven
6530's may be addressed, giving 7168 x 8 bits of
contiguous ROM.
RAM - 64 Bytes (512 Bits)
A 64 x 8 static RAM is contained on the 6530. It is
addressed by AO-A5 (Byte Select), RSO, A6, A7, A8, A9
and, depending on the number of chips in the system,
CS1 and CS2.
Internal Peripheral Registers
There are four internal registers, two data direction
registers and two peripheral I/O data registers. The two
data direction registers (A side and B side) control the
direction of the data into and out of the peripheral pins.
A "1" written into the Data Direction Register sets up
the corresponding peripheral buffer pin as an output.
Therefore, anything then written into the I/O Register
will appear on that corresponding peripheral pin. A "a"
written into the DDR inhibits the output buffer from
transmitting data to or from the I/O Register. For
example, a "1" loaded into data direction register A,
position 3, sets up peripheral pin PA3 as an output. If a
"a" had been loaded, PA3 would be configured as an
input and remain in the high state. The two data I/O
registers are used to latch data from the Data Bus
during a Write operation until the peripheral device
can read the data supplied by the microprocessor
array.
Interval Timer
The Timer section of the 6530 contains three basic
parts: prel iminary divide down reg ister, prog rammable
8-bit register and interrupt logic. These are illustrated
in Figure 4.
The interval timer can be programmed to count up
to 256 time intervals. Each time interval can be either
1T, 8T, 64T or 1024T increments, where T is the system
clock period. When a full count is reached, an interrupt
flag is set to a logic "1." After the interrupt flag is set the
internal clock begins counting down to a maximum of
-255T.Thus, after the interruptflag is set, a Read ofthe
timer will tell how long since the flag was set up to a
maximum of 255T.
The 8 bit system Data Bus is used to transfer data to
and from the Interval Timer. If a count of 52 time
intervals were to be counted, the pattern aa1 1 a1 aa
would be put on the Data Bus and written into the
Interval Time register.
At the same time that data is being written to the
Interval Timer, the counting intervals of 1,8,64, 1024T
are decoded from address lines AO and A1. During a
Read or Write operation address line A3 controls the
interrupt capability of PB7, i.e.,A3 = 1 enables IRO on
PB7,A3 =0 disables IROon PB7.When PB7 istobe
used as an interrupt flag with the interval timer it should
be programmed as an input. If PB7 is enabled by A3
and an interrupt occurs PB7 will go low. When the
timer is read prior to the interrupt flag being set, the
number of time intervals remaining will be read, i.e., 51,
50,49, etc.
I
2-101

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