|
|
PDF 6522 Data sheet ( Hoja de datos )
| Número de pieza | 6522 | |
| Descripción | VERSATILE INTERFACE ADAPTER | |
| Fabricantes | Commodore | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 6522 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
, . . , commodore
~ aamicanduct:or group
~UYAJ@@
MPS
6522
VERSATILE
INTERFACE
ADAPTER
6522 VERSATILE INTERFACE ADAPTER
DESCRIPTION
The 6522 Versatile Interface Adapter (VIA) provides all of the capability of the 6520.1 n addition, this
device contains a pair of very powerful interval timers, a serial-to-parallellparallel-to-serial shift
register and input data latching on the peripheral ports. Expanded handshaking capability allows
control of bi-directional data transfers between VIA's in multiple processor systems.
Control of peripheral devices is handled primarily through two 8-bit bi-directional ports. Each of
these lines can be programmed toactaseitheran inputoran output.Also, several peripheralI/O lines
can be controlled directly from the interval timers for generating programmable-frequency square
waves and for counting externally generated pulses. To facilitate control of the many powerful
features of this chip, the internal registers have been organized into an interrupt flag register, an
interrupt enable register and a pair of function control registers.
FEATURES
• Very powerful expansion of basic 6520 capability.
• N channel, depletion load technology, single +5V supply.
• Completely static and TIL compatible.
• CMOS compatible peripheral control lines.
• Expanded "handshake" capability allows very positive
control of data transfers betvoJeen processor
and peripheral devices.
6522 Interface Diagram
To
650X
8 Bit
Data Bus
R/W
Clock
Register
& Chip
Selects
IRQ
6522
--..
Control
8 Bi:
Port
8 Bit
Port
Control
To
Peripheral
Devices
6522
vSS CA1
PAO CA2
PA1 RSO
PA2 RS1
PA3 RS2
PA4 RS3
PA5 RES
PA6 DO
PA7 01
PBO 02
PB1 03
PB2 04
PB3 05
PB4 06
PB5 07
PB6 ¢2
PB7 CS1
CB1 CS2
CB2 R/W
VCC IRQ
2-50
1 page  
MPS
6522
TIMER 1
Introduction
Interval Timer T1 consists of two 8-bit latches and a 16-bit
counter. The latches are used to store data which is to be
loaded into the counter. After loading, the counter decrements
at system clock rate, i.e., under control of the clock applied to
the Phase Two input pin. Upon reaching zero, an interrupt flag
will be set, and iTiQ will go low. The timer will then disable any
further interrupts, or will automatically transfer the contents of
the latches into the counter and will continue to decrement. In
addition, the timer can be instructed to invert the output signal
on a peripheral pin each time it "times-out." Each of these
modes is discussed separately below.
Writing the Timer 1 Registers
The operations which take place when writing to each of the
four T1 addresses are as follows:
Transfer low order latch into low order
RS3 RS2 RS1 RSO Operation (R/W = L)
L H L L Write into low order latch.
L H L H Write into high order latch.
Write into high order counter.
Transfer low order latch into low order counter.
Reset Tl interrupt flag.
L H H L Write low order latch.
L H H H Write high order latch.
Reset Tl interrupt flag.
Note that the processor does not write directly Into the low
order counter (T1 Col). Instead, this half of the counter is loaded
automatically from the low order latch when the processor
writes into the high order counter. In fact, it may not be
necessary to write to the low order counter in some appl ications
since the timing operation is triggered by writing to the high
order counter.
The second set of addresses allows the processor to write
into the latch register without affecting the count-down in
progress. This is discussed in detail below.
Reading the Timer 1 Registers
For reading the Timer 1 registers, the four addresses relate
directly to the four registers as follows:
RS3 RS2 RS1 RSO Operation (R/W = HI
L H L L Read Tl low order counter.
Reset Tl interrupt flag.
L H L H Read Tl high order counter.
L H H L Read Tl low order latch.
L H H H Read Tl high order latch.
TImer 1 Operating Modes
Two bits are provided in the Auxiliary Control Register to
allow selection of the T1 operating modes. These bits and the
four possible modes are as follows:
ACR7 ACR6
Output "Free-Run"
Enable Enable Mode
0 0 Generate a single time-out interrupt each time Tl is
loaded. PB7 disabled.
0 1 Generate continuous interrupts. PB7 disabled.
1 0 Generate a single interrupt and an output pulse on PB7
for each Tl load operation.
1 1 Generate continuous interrupts and a square wave
output on PB7.
Timer 1 One-Shot Mode
The interval timer one-shot mode allows generation of a
single interrupt for each timer load operation. As with any
interval timer, the delay between the "write T1 C-H" operation
and generation of the processor interrupt is a direct function of
the data loaded into the timing counter. In addition to gener-
ating a single interrupt, Timer 1 can be programmed to produce
a single negative pulse on the PB7 peripheral pin. With the
output enabled (ACR&=1) a "write T1 C-H" operation will cause
PB7 to go low. PB7 will return high when Timer 1 times out. The
result is a single programmable width pulse.
NOTE
PB7 will act as an output if DDRB7 = 1 or if ACR7 = 1. However, if
both DDRB7 and ACR7 are logic 1, PB7 will be controlled from Timer 1
and ORB7 will have no effect on the pin.
In the one-shot mode, writing into the high order latch has no
effect on the operation of Timer 1. However, it will be necessary
to assure that the low order latch contains the proper data
before initiating the count-down with a "write T1 C-H" operation.
When the processor writes into the high order counter, the T1
interrupt flag will be cleared, the contents of the low order latch
will be transferred into the low order counter, and the timer will
begin to decrement at system clock rate. If the PB7 output is
enabled, this signal will go low on the phase two following the
write operation. When the counter reaches zero; the T1 interrupt
flag will be set, the IRQ pin will go low (interrupt enabled), and
the signal on PB7 will go high. At this time the counter will
continue to decrement at system clock rate. This allows the
system processor to' read the contents of the counter to
determine the time since interrupt. However, the T1 interrupt
flag cannot be set again unless it has been cleared as
described on page 13 of this specification.
Timing for the 6522 interval timer one-shot modes is shown
in Figure 5.
Phase Two Clock
WritOepTetrCat-iHonl ~L----------Ilf---------------
IRQ Output - - - - - - - - - - - - - - - - I f - - - - - - - - - , L -_ _ _ _ _ _ __
PB7 Output _ _ _ _.....,
I I I I IIo FF
FE FD
FC
Notes:
1. RtW-L,CS2-L,CS1-H,RS3-LRS2-H,RS1-RSO-H.
·1
Figure 5. Interval Timer "One-shot" Mode Timing Sequence.
2-54
5 Page 
MPS
6522
1. PA Latch Enable
The 6522 provides input latching on both the PA and PB
ports. In this mode, the data present on the peripheral A input
pins will be latched within the chip when the CA1 interrupt flag
is set. Reading the PA port will result in these latches being
transferred into the processor. As long as the CA1 interrupt flag
is set, the data on the peripheral pins can change without
affecting the data in the latches. This input latching can be used
with any of the CA2 input or output modes.
It is important to note that on the PA port, the proCessor
always reads the data on the peripheral pins (as reflected in the
latches). For output pins, the processor still reads the latches.
This mayor may not reflect the data currently in the ORA. Proper
system operation requires careful planning on the part of the
system designer if input latching is combined with output pins
on the peripheral ports.
aInput latching is enabled by setting bit in the Auxiliary
Control Register to a logic 1.As long as this bit isaO, the latches
will directly reflect the data on the pins.
2. PB Latch Enable
Input latching on the PB port is controlled in the same
manner as that described for the PA port. However, with the
peripheral B port the input latch will store either the voltage on
the pin or the contents ofthe Output Register (ORB) depending
on whether the pin is programmed to act as an input or an
output. As with the PA port, the processor always reads the input
latches.
3. Shift Register Control
The Shift Register operating mode is selected as follows:
ACR4
0
0
0
0
1
1
1
1
ACR3
0
0
1
1
0
0
1
1
ACR2
0
1
0
1
0
1
0
1
Mode
Shift Register Disabled.
Shift in under control of Timer 2.
Shift in under control of system clock.
Shift in under control of extemal clock pulses.
Free-running output at rate determined by Timer 2.
Shift out under control of Timer 2.
Shift out under control of the system clock.
Shift out under control of external clock pulses.
4. T2 Control
Timer 2 operates in two modes. If ACR5 = a, T2 acts as an
interval timer in the one-shot mode. If ACR5 = 1, Timer 2 acts to
count a predetermined number of pulses on pin PB6.
5. T1 Control
Timer 1 operates in the one-shot or free-running mode with
the PB7 output control enabled or disabled. These modes are
selected as follows:
ACR7
0
0
1
1
ACR8
0
1
0
1
Mode
One-shot mode - Output to PB7 disabled.
Free-running mode -Output to PB7 disabled.
One-shot mode - Output to PB7 enabled.
Free-running mode. Output to PB7 enabled.
APPLICATION OF THE 6522
The 6522 represents a significant advance in general-
purpose microprocessor I/O. Unfortunately, its many powerful
features, coupled with a set of very flexible operating modes,
cause this device to appear to be very complex at first glance.
wever, a detailed analysis will show that theVIA is organized to
allow convenient control of these powerful features. This
section seeks to assist the system designer in his under-
standing of the 6522 by illustrating how the device can be used
in microprocessor-based systems.
A. Control of 6522 Interrupts
Organization of the 6522 interrupt flags into a single register
greatly facilitates the servicing of interrupts from this device.
Since there is only one IRQ output for the seven possible
sources of interrupt within the chip, the processor must exam-
ine these flags to determine the cause of an interrupt. This is
best accomplished by first transferring the contents of the flag
register into the accumulator. At this time it may be necessary to
mask off those flags which have been disabled in the Interrupt
Enable Register. This is particularly important for the edge
detecting inputs where the flags may be set whether or not the
interrupting function has been enabled. Masking off those flags
can be accomplished by performing an AND operation be-
tween the IE R and the accumulator or by performing an "AN D
IMMEDIATE." The second byte of this AND # instruction
should specify those flags which correspond to interrupt
functions which are to be serviced.
If the N flag is set after these operations, an active interrupt
exists within the chips. This interrupt can be detected with a
series of shift and branch instructions.
Clearing interrupt flags is accomplished very conveniently
by writing a logic 1 directly into the appropriate bit of the
Interrupt Flag Register. This can be combined with an interrupt
enable or disable operation as follows:
LDA #@1 001 0000 initialize accumulator
STA IFR
clear interrupt flag
STA IER
set interrupt enable flag
or:
LDA #@00001 000
STA IFR
STA IFR
initialize accumulator
clear interrupt flag
disable interrupt
Another very useful technique for clearing interrupt flags is to
simply transfer the contents of the flag register back into this
register as follows:
LDAIFR
transfer IFR to accumulator
STA IFR
clear flags corresponding to active
interrupts
After completion of this operation the accumulator will still
contain the interrupt flag information. Most important, writing
into the flag register clears only those flags which are already
set. This eliminates the possibility of inadvertently clearing a
flag while it is being set.
B. Use of Timer 1
Timer 1 represents one of the most powerful features of the
6522. The ability to generate very evenly spaced interrupts and
the ability to control the voltage on PB7 makes this timer
particularly valuable in various timing,data detection and wave-
form generation applications.
Tlme-of-Day Clock Applications
An important feature of many 'systems is the time-of-day
clock. In microprocessor-based systems the time of day is
usually maintained in memory and is updated in an interrupt
service routine. A regular processor interrupt will then assure
that this time of day will always be available when it is needed in
the main program.
2-60
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 6522.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 6520 | PERIPHERAL ADAPTER | Commodore |
| 6522 | VERSATILE INTERFACE ADAPTER | Commodore |
| 6523 | TRI-PORT INTERFACE | Commodore |
| 65245 | OCTAL BUS TRANSCEIVER | Commodore |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |