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6501 Schematic ( PDF Datasheet ) - Commodore

Teilenummer 6501
Beschreibung ONE-CHIP MICROCOMPUTER
Hersteller Commodore
Logo Commodore Logo 




Gesamt 23 Seiten
6501 Datasheet, Funktion
, . .commodore
~ aarnlconduCl:ar group
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MPS
6500/1
ONE-CHIP
MICROCOMPUTER
8500/1 ONE-CHIP MICROCOMPUTER
INTRODucnoN
The MOS Technology 6500/1 Is a complete, high-performance 8-blt NMOS microcomputer on a single chip, and
Is totally upward/downward software compatible with all members of the 6500 family.
The 650011 consists of a 6502 CPU, an Internal clock oscillator, 2048 bytes of Read Only Memory (ROM), 64 bytes
of Random Access Memory (RAM) and flexible Interface circuitry. The· interface circuitry includes a 18-blt
programmable counter/latch with four operating modes, 32 bidirectional Input/output lines (Including two edge-
sensitive lines), five Interrupts and a counter I/O line.
PRODUCT SUPPORT
To allow prototype clrCl~lt development, Mos Tech-
nology offers a PROM compatible 64-pln Emulator de-
vice. This device provides all 650011 Interface lines
plus routing the address bus, data bus, and asso-
ciated control lines off the chip to be connected to
external memory.
Order
Number
ORDERING INFORMATION
Package Frequency Temperature
Type Option
Range
MPS65OOI1
Plastic 1 MHz
MCS6500/1 Ceramic 1 MHz
MPS65OOI1A Plastic 2 MHz
MCS65OOI1A Ceramic 2 MHz
MCS65OOI1E Emulator Device 1MHz
'MCS65OOI1EA Emulator Device 2MHz
O°C to 70°C
O°C to 70°C
O°C to 70°C
O°C to 70°C
Note: The RC frequency option is available only in the
1 MHz 6500/1.
XTU
)(flO
RES
Rgj
vee
vss
VRR
¢a;> PAO-PA7
¢a~ P8(H2B7
¢a ~ pc()'PC7
¢a::> POOPD7
CNTR
FEATURES
• 6502 CPU
-Software upward/downward compatibility
-Decimal or binary arithmetic modes
-13 addressing modes
-True direct and indirect indexing
-Memory addressable 110
• 2048 x 8 mask programmable ROM
• 64 x 8 static RAM
• 32 bi<iirectional TIL compatible 110 lines (4 ports)
• 1 bi<iirectional TIL compatible counter I/O line
• 16-bit programmable counter/latch with four
modes
-Interval Timer -Event Counter
-Pulse Generator -Pulse Width Measurement
• Five Interrupts
-Reset
-Non·maskable
-Two external edge sensitive
-Counter
• 1 of 3 frequency references
-Crystal -Clock -RC (resistor only)
• 4 MHz max crystal or clock external frequency
• 2 MHz or 1 MHz internal clock
• 1 /Ls minimum instruction execution
• N-channel, silicon gate, depletion load technology
• Single + 5V power supply
• 500 mW operating power
• Separate power pin for RAM
• 40 pin DIP
• 64 pin PROM compatible Emulator device
Interface Diagram
2-2






6501 Datasheet, Funktion
MPS
6500/1
SIGNAL DESCRIPTIONS
SIGNAL PIN
NAME NO. DESCRIPTION
VCC
VRR
VSS
XTLI
XTLO
m
30 Main power supply + 5V
Separate power pin for RAM. In the
event that VCC power Is lost, this
power retains RAM data.
12 Signal ground
10 Crystal, clock or RC network Input
for Internal clock oscillator.
11 Crystal or RC network output from
Internal clock oscillator.
39 The Reset Input Is used to Initialize
the 6500/1. This signal must not
transition from low to high for at
least eight cycles after VCC
reaches operating range and the In-
ternal oscillator has stabilized.
+ 10V Input enables the test mode.
SIGNAL PIN
NAME NO. DESCRIPTION
'fimT
40 A negative going edge on the Non-
Maskable Interrupt signal requests
that a nO[l;,maskable Interrupt be
generated within the CPU.
PAO-PA7 38-31 Four 8 bit ports used for either
PBO-PB7 29-22 input/output. Each line consists
PCO-PC7 20-13 of an active transistor to VSS and
a passive pull-up to + 5V. The two
PDO-PD7 9-2 lower bits of the PA port (PAO and
PA1) also serve as edge detect In-
puts with maskable Interrupts.
CNTR
21 This line Is used as a Counter In-
put/output line. CNTR Is an Input In
the Event Counter and Pulse Width
Measurement modes and Is an out·
put In the Interval Timer and Pulse
Generator modes.
VRR
P07
PD6
P05
P04
P03
P02
P01
POO
XTU
XTLO
VSS
PC7
PCS
PC5
PC4
PC3
PC2
PC1
PCO
1 NMI
2 RES
3 PAO
4 37 PA1
5 36 PA2
6 35 PA3
7 34 PA4
8 33 PA5
9 32 PA6
10 31 PA7
11 30 VCC
12 29 PBO
13 28 PB1
14 27 PB2
15 26 PB3
16 25 PB4
17 24 PB5
18 23 PB6
19 22 PB7
20 21 CNTR
Pin Configuration
2-7

6 Page









6501 pdf, datenblatt
MPS
6500/1
MOS PAPER TAPE FORMAT
The paper tape which should be used Is 1" wide paper tape using 7 or 8 bit ASCII code. Each byte of data to be
stored Is converted to two half bytes. The half bytes (whose possible values are 0 to FHEX) are translated Into their
ASCII equivalents and written onto paper tape In this form.
Each record output begins with a semicolon (";") character (ASCII 3B) to mark the start of a valid record. The
next byte transmitted (Range: 1 to 18HEX) Is the number of data bytes contained In the record. The record's star-
ting address high (1 byte, 2 characters), starting address low (1 byte, 2 characters), and data (usually 24 bytes, 48
characters) follow. Each record Is terminated by the record's check-sum' (2 bytes, 4 characters), a carriage return
(ASCII 00), Line Feed (ASCII OA), and six "NULL" characters (ASCII 0). No other characters, such as rubouts, are
allowed anywhere.
The last record transmitted has zero data bytes (indicated by ;00). The starting address field is replaced ~y a
four digit HEX number representing the total number of data records contained ill the transmission, followed by
the records usual check-sum digits. An "XOFF" character ends the transmission.
EXAMPLE:
;180000FFEEODCCBBAAOO99887766554433221122334455667788990AFC;OOOOO10001
All records must be punched in consecutive order and the data at each address must be completely and ex-
pliCitly defined. All Invalid data will be Ignored and zeros substituted. Additional information as described In sec-
tion entitled "TITLE CARDS" should be provided at transmission.
I
Commodore Semiconductor Group reserves the right to make changes to any products herein to improve
reliability, function or design. Commodore Semiconductor Group does not assume any liability arising out of
the application or use of any product or circuit described herein; neither does it convey any license under its
patent rights nor the rights of others.
2-13

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