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MT8HTF12864AY Schematic ( PDF Datasheet ) - Micron

Teilenummer MT8HTF12864AY
Beschreibung 1GB DDR2 SDRAM UDIMM
Hersteller Micron
Logo Micron Logo 




Gesamt 18 Seiten
MT8HTF12864AY Datasheet, Funktion
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM UDIMM
MT8HTF3264AY – 256MB
MT8HTF6464AY – 512MB
MT8HTF12864AY – 1GB
Features
240-pin, unbuffered dual in-line memory module
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, PC2-6400, or PC2-8500
256MB (32 Meg x 64), 512MB (64 Meg x 64),
or 1GB (128 Meg x 64
VDD = VDDQ = 1.8V
VDDSPD = 1.7–3.6V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Multiple internal device banks for concurrent
operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Programmable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
Single rank
Figure 1: 240-Pin UDIMM (MO-237 R/C A and D)
PCB height: 30.0mm (1.18in)
Options
Operating temperature
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)1
Package
240-pin DIMM (lead-free)
Frequency/CL2
1.875ns @ CL = 7 (DDR2-1066)3
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)4
5.0ns @ CL = 3 (DDR2-400)
Marking
None
I
Y
-1GA
-80E
-800
-667
-53E
-40E
Notes:
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Available only in 1GB, Rev. E devices.
4. Not recommended for new designs.
Table 1: Key Timing Parameters
Speed
Grade
-1GA
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-8500
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 7
1066
Data Rate (MT/s)
CL = 6 CL = 5 CL = 4
800 667 533
800 800 533
800 667 533
667 553
– – 553
– – 400
CL = 3
400
400
400
400
400
400
tRCD
(ns)
13.125
12.5
15
15
15
15
tRP
(ns)
13.125
12.5
15
15
15
15
tRC
(ns)
58.125
57.5
60
60
55
55
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.






MT8HTF12864AY Datasheet, Funktion
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Descriptions
Table 7: Pin Descriptions (Continued)
Symbol
SDA
RDQSx,
RDQS#x
Err_Out#
VDD/VDDQ
VDDSPD
VREF
VSS
NC
NF
NU
RFU
Type
I/O
Output
Output
(open drain)
Supply
Supply
Supply
Supply
Description
Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
the I2C bus.
Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disa-
bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
Parity error output: Parity error found on the command and address bus.
Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-
ule VDD.
SPD EEPROM power supply: 1.7–3.6V.
Reference voltage: VDD/2.
Ground.
No connect: These pins are not connected on the module.
No function: These pins are connected within the module, but provide no functionality.
Not used: These pins are not used in specific module configurations/operations.
Reserved for future use.
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
6 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.

6 Page









MT8HTF12864AY pdf, datenblatt
IDD Specifications
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 256MB
Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8)
component data sheet
Parameter
Symbol -667 -53E -40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
IDD0
720 640 600 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Ad-
dress bus inputs are switching; Data pattern is same as IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
IDD1
IDD2P
800 720 680 mA
40 40 40 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
IDD2Q
320 280 200 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
IDD2N
320 280 240 mA
Active power-down current: All device banks open; tCK = Fast PDN exit IDD3PF 240 200 160 mA
tCK (IDD); CKE is LOW; Other control and address bus inputs MR[12] = 0
are stable; Data bus inputs are floating
Slow PDN exit IDD3PS 48 48 48
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus inputs
are switching
IDD3N
400 320 240 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
IDD4W
1520 1280 1000 mA
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD4R
1440 1200 920 mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD5
1440 1360 1320 mA
Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
IDD6
40 40 40 mA
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.

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