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MT5VDDT3272A Schematic ( PDF Datasheet ) - Micron

Teilenummer MT5VDDT3272A
Beschreibung 256MB DDR SDRAM UDIMM
Hersteller Micron
Logo Micron Logo 




Gesamt 12 Seiten
MT5VDDT3272A Datasheet, Funktion
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Features
DDR SDRAM UDIMM
MT5VDDT872A – 64MB1
MT5VDDT1672A – 128MB2
MT5VDDT3272A – 256MB2
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 184-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC2100, PC2700, or PC3200
• 64MB (8 Meg x 72), 128MB (16 Meg x 72), and
256MB (32 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +2.5V
(-40B: VDD = VDDQ = +2.6V)
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR)
2n-prefetch architecture
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-synchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Single rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes:
64MB = 15.625µs and 128MB, 256MB = 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
• Gold edge contacts
Figure 1: 184-Pin UDIMM (MO-206 R/C C)
PCB height: 31.75mm (1.25in)
Options
• Operating temperature3
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)
• Package
184-pin DIMM (standard)
184-pin DIMM (Pb-free)
• Memory clock, speed, CAS latency
5.0ns (200 MHz), 400 MT/s, CL = 3.0
6.0ns (167 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2.0
7.5ns (133 MHz), 266 MT/s, CL = 2.0
7.5ns (133 MHz), 266 MT/s, CL = 2.5
Marking
None
I
G
Y
-40B
-335
-262
-26A
-265
Notes: 1. End of life.
2. Not recommended for new designs.
3. Contact Micron for industrial temperature
module offerings.
Table 1: Key Timing Parameters
Speed
Grade
-40B
-335
-262
-26A
-265
Industry
Nomenclature
Data Rate (MT/s)
CL = 3 CL = 2.5 CL = 2
tRCD
(ns)
tRP
(ns)
tRC
(ns)
Notes
PC3200
PC2700
PC2100
PC2100
PC2100
400 333 266
15
15
55
333 266
18
18
60 1
266 266
15
15
60
266 266
20
20
65
266 200
20
20
65
Notes: 1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications;
actual DDR SDRAM device specifications are 15ns.
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.






MT5VDDT3272A Datasheet, Funktion
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
General Description
General Description
The MT5VDDT872A, MT5VDDT1672A, and MT5VDDT3272A are high-speed CMOS,
dynamic random access 64MB, 128MB, and 256MB memory modules organized in a x72
configuration. These modules use DDR SDRAM devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the
module, permanently disabling hardware write protect.
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.

6 Page









MT5VDDT3272A pdf, datenblatt
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Module Dimensions
Module Dimensions
Figure 3: 184-Pin DDR UDIMM
Front view
133.50 (5.256)
133.20 (5.244)
3.18 (0.125)
MAX
2.0 (0.079) R
(4X)
2.5 (0.098) D
(2X)
2.31 (0.091) TYP
2.21 (0.087) TYP
1.0 (0.039) TYP
U1 U2 U3 U4 U5
Pin 1
1.27 (0.05)
TYP
64.77 (2.55)
TYP
1.02 (0.04)
TYP
0.9 (0.035) R
6.35 (0.25) TYP
120.65 (4.75)
49.53 (1.95)
TYP
Back view
31.90 (1.256)
31.60 (1.244)
U6
17.78 (0.70)
TYP
Pin 92
1.37 (0.054)
1.17 (0.046)
No components this side of module
Pin 184
73.28 (2.88)
TYP
10.0 (0.394)
3.8 (0.15) TYP
TYP
Pin 93
Notes:
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for addi-
tional design dimensions.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth
herein. Although considered final, these specifications are subject to change, as further product development and data
characterization sometimes occur.
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.

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