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MT4HTF6464AY Schematic ( PDF Datasheet ) - Micron

Teilenummer MT4HTF6464AY
Beschreibung 512MB DDR2 SDRAM UDIMM
Hersteller Micron
Logo Micron Logo 




Gesamt 19 Seiten
MT4HTF6464AY Datasheet, Funktion
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM UDIMM
MT4HTF1664AY – 128MB
MT4HTF3264AY – 256MB
MT4HTF6464AY – 512MB
Features
240-pin, unbuffered dual in-line memory module
(UDIMM)
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
128MB (16 Meg x 64), 256MB (32 Meg x 64),
512MB (64 Meg x 64)
VDD = VDDQ = 1.8V
VDDSPD = 1.7–3.6V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Multiple internal device banks for concurrent
operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Programmable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
Single rank
Figure 1: 240-Pin UDIMM (MO-237 R/C C)
Module height 30.0mm (1.18in)
Options
Operating temperature
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)1
Package
240-pin DIMM (lead-free)
Frequency/CL2
2.5ns @ CL = 5 (DDR2-800)4
2.5ns @ CL = 6 (DDR2-800)4
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)3
5.0ns @ CL = 3 (DDR2-400)3
Marking
None
I
Y
-80E
-800
-667
-53E
-40E
Notes:
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Contact Micron for product availability.
4. Not available in 128MB and 256MB.
Table 1: Key Timing Parameters
Speed
Grade
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 6
800
800
Data Rate (MT/s)
CL = 5
CL = 4
800 533
667 533
667 553
553
400
CL = 3
400
400
400
400
400
tRCD
(ns)
12.5
15
15
15
15
tRP
(ns)
12.5
15
15
15
15
tRC
(ns)
55
55
55
55
55
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.






MT4HTF6464AY Datasheet, Funktion
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
S0#
VSS
DQS0
DQS0#
DM0
DQS1
DQS1#
DM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQS3
DQS3#
DM3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
U1
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
U2
DQS4
DQS4#
DM4
DQS5
DQS5#
DM5
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS6#
DM6
DQS7
DQS7#
DM7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
U3
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
U4
BA[2/1:0]
A[12:0]
RAS#
CAS#
WE#
CKE0
ODT0
Vss
Vss
BA[2:0]: DDR2 SDRAM
A[12:0]: DDR2 SDRAM
RAS#: DDR2 SDRAM
CAS#: DDR2 SDRAM
WE#: DDR2 SDRAM
CKE0: DDR2 SDRAM
ODT0: DDR2 SDRAM
SCL
CK1
CK1#
U5
SPD EEPROM
WP A0 A1 A2
VSS SA0 SA1 SA2
CK0
CK0#
SDA
DDR SDRAM x 2
CK2
CK2#
DDR SDRAM x 2
VDDSPD
VDD/VDDQ
VREF
VSS
SPD EEPROM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN
6 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.

6 Page









MT4HTF6464AY pdf, datenblatt
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 11: DDR2 IDD Specifications and Conditions – 256MB
Values shown for MT47H32M16 DDR2 SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16)
component data sheet
Parameter
-80E/
Symbol -800 -667 -53E -40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0
540 480 440 440 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
IDD1
IDD2P
660 600 540 520 mA
28 28 28 28 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); IDD2Q 260 220 180 160 mA
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is IDD2N 280 240 200 180 mA
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open; tCK
= tCK (IDD); CKE is LOW; Other control and address bus in-
puts are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
IDD3P
160 140 120 100 mA
48 48 48 48
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
IDD3N 300 280 240 200 mA
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
IDD4W 1180 1000 820 640 mA
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst IDD4R 1100 940 780 620 mA
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD5
920 740 700 680 mA
Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD6 28 28 28 28 mA
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.

12 Page





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