|
|
PDF MT36HTJ51272 Data sheet ( Hoja de datos )
| Número de pieza | MT36HTJ51272 | |
| Descripción | 4GB DDR2 SDRAM Registered DIMM | |
| Fabricantes | Micron | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MT36HTJ51272 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Features
DDR2 SDRAM Registered DIMM (RDIMM)
MT36HTJ51272(P) – 4GB
For the latest data sheet and for component data sheets, refer to Micron's Web site: www.micron.com
Features
• Supports 95°C with double refresh
• 240-pin, registered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200, or
PC2-5300
• Supports ECC error detection and correction
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Dual rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Figure 1: 240-Pin DIMM (MO-237 R/C “K”)
Height: 30mm (1.18in)
Options
Marking
• Parity
• Package
240-pin DIMM (lead-free)
• Frequency/CAS latency1
3.0ns @ CL = 5 (DDR2-667)2
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB height
30mm (1.18in)
P
Y
-667
-53E
-40E
Notes: 1. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
2. Contact Micron for product availability.
Table 1: Key Timing Parameters
Speed
Grade
-667
-53E
-40E
Table 2:
Industry Nomenclature
PC2-5300
PC2-4200
PC2-3200
Addressing
Data Rate (MT/s)
CL = 5
667
–
–
CL = 4
533
533
400
CL = 3
400
400
400
tRCD
(ns)
15
15
15
tRP
(ns)
15
15
15
tRC
(ns)
55
55
55
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
4GB
8K
16K (A0–A13)
8 (BA0–BA2)
1KB
1Gb (256 Meg x 4)
2K (A0–A9, A11)
2 (S0#, S1#)
PDF: 09005aef822553c2/Source: 09005aef822553af
HT36HTJ51272.fm - Rev. B 7/06 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
General Description
General Description
The MT36HTJ51272 DDR2 SDRAM module is a high-speed, CMOS, dynamic random-
access 4GB memory module organized in a x72 configuration. This DDR2 SDRAM
module uses internally configured 8-bank (1Gb) DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-
wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
PLL and Register Operation
DDR2 SDRAM modules operate in registered mode, where the command/address input
signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM
devices on the following rising clock edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL) on the module receives and redrives the differential clock signals
(CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize system and
clock loading. PLL clock timing is defined by JEDEC specifications and ensured by use of
the JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Serial Presence-Detect Operation
DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
PDF: 09005aef822553c2/Source: 09005aef822553af
HT36HTJ51272.fm - Rev. B 7/06 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
5 Page 
4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
Table 13: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Symbol
tAA
tBUF
tDH
tF
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
fSCL
tSU:DAT
tSU:STA
tSU:STO
tWRC
Min
0.2
1.3
200
–
0
0.6
0.6
–
1.3
–
–
100
0.6
0.6
–
Max
0.9
–
–
300
–
–
–
50
–
0.3
400
–
–
–
10
Units
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
Notes
1
2
2
3
4
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid STOP condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to the pull-up
resistor, and the EEPROM does not respond to its slave address.
PDF: 09005aef822553c2/Source: 09005aef822553af
HT36HTJ51272.fm - Rev. B 7/06 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MT36HTJ51272.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT36HTJ51272 | 4GB DDR2 SDRAM Registered DIMM | Micron |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |