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MT18VDVF12872D Schematic ( PDF Datasheet ) - Micron

Teilenummer MT18VDVF12872D
Beschreibung 1GB DDR SDRAM VLP Registered DIMM
Hersteller Micron
Logo Micron Logo 




Gesamt 30 Seiten
MT18VDVF12872D Datasheet, Funktion
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Features
DDR SDRAM VLP Registered DIMM
MT18VDVF6472D – 512MB
MT18VDVF12872D – 1GB
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/modules
Features
• 184-pin, very low profile dual in-line memory
module (VLP DIMM)
• Fast data transfer rates: PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Supports ECC error detection and correction
• 512MB (64 Meg x 72) and 1GB (128 Meg x 72)
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes
• 7.8125µs maximum average periodic refresh
interval
• Serial presence detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
• Dual rank
Figure 1: 184-Pin VLP DIMM (MO-206)
Very Low Profile Height 0.72in (18.29mm)
Options
Marking
• Package
184-pin DIMM (standard)
184-pin DIMM (lead-free)1
• Memory clock, speed, CAS latency2
6ns (166MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
• PCB height
Very Low-Profile 0.72in (18.29mm)1
G
Y
-335
-2621
-26A1
-265
Notes:1. Contact Micron for product availability.
2. CL = CAS (READ) latency; registered mode
adds one clock cycle to CL.
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_1.fm - Rev. A 8/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.






MT18VDVF12872D Datasheet, Funktion
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 3: Pin Assignment
184-pin DIMM Front
184-Pin DIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VREF 24 DQ17 47 DQS8 70 VDD 93 VSS 116 VSS 139 VSS 162 DQ47
2 DQ0 25 DQS2 48 A0 71 NC 94 DQ4 117 DQ21 140 DM8 163 NC
3 VSS 26 VSS 49 CB2 72 DQ48 95 DQ5 118 A11 141 A10 164 VDDQ
4 DQ1 27 A9 50 VSS 73 DQ49 96 VDDQ 119 DM2 142 CB6 165 DQ52
5 DQS0 28 DQ18 51 CB3 74 VSS 97 DM0 120 VDD 143 VDDQ 166 DQ53
6 DQ2 29 A7 52 BA1 75 DNU 98 DQ6 121 DQ22 144 CB7 167 NC
7 VDD 30 VDDQ 53 DQ32 76 DNU 99 DQ7 122 A8 145 VSS 168 VDD
8 DQ3 31 DQ19 54 VDDQ 77 VDDQ 100 VSS 123 DQ23 146 DQ36 169 DM6
9 NC 32 A5 55 DQ33 78 DQS6 101 NC 124 VSS 147 DQ37 170 DQ54
10 RESET# 33 DQ24 56 DQS4 79 DQ50 102 NC 125 A6 148 VDD 171 DQ55
11 VSS 34 VSS 57 DQ34 80 DQ51 103 NC 126 DQ28 149 DM4 172 VDDQ
12 DQ8 35 DQ25 58 VSS 81 VSS 104 VDDQ 127 DQ29 150 DQ38 173 NC
13 DQ9 36 DQS3 59 BA0 82 NC 105 DQ12 128 VDDQ 151 DQ39 174 DQ60
14 DQS1 37 A4 60 DQ35 83 DQ56 106 DQ13 129 DM3 152 VSS 175 DQ61
15 VDDQ 38 VDD 61 DQ40 84 DQ57 107 DM1 130 A3 153 DQ44 176 VSS
16 DNU 39 DQ26 62 VDDQ 85 VDD 108 VDD 131 DQ30 154 RAS# 177 DM7
17 DNU 40 DQ27 63 WE# 86 DQS7 109 DQ14 132 VSS 155 DQ45 178 DQ62
18 VSS 41 A2 64 DQ41 87 DQ58 110 DQ15 133 DQ31 156 VDDQ 179 DQ63
19 DQ10 42 VSS 65 CAS# 88 DQ59 111 CKE1 134 CB4 157 S0# 180 VDDQ
20 DQ11 43 A1 66 VSS 89 VSS 112 VDDQ 135 CB5 158 S1# 181 SA0
21 CKE0 44 CB0 67 DQS5 90 DNU 113 NC 136 VDDQ 159 DM5 182 SA1
22 VDDQ 45 CB1 68 DQ42 91 SDA 114 DQ20 137 CK0 160 VSS 183 SA2
23 DQ16 46 VDD 69 DQ43 92 SCL 115 A12 138 CK0# 161 DQ46 184 VDDSPD
Figure 2: Pin Locations
Front View
Very Low Profile
U1 U2 U3 U4 U5
U6
U8 U9 U10 U11
U7
PIN 1
Back View
PIN 52
U12
U13
U14
U15 U16
U17
PIN 53
PIN 92
U18 U19 U20 U21 U22
PIN 184
PIN 145
PIN 144
Indicates a VDD or VDDQ pin
Indicates a VSS pin
PIN 93
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.

6 Page









MT18VDVF12872D pdf, datenblatt
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Mode Register Definition
Read Latency
The READ latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first bit of output data. The latency can be set to 2 or 2.5
clocks, as shown in Figure 5, "CAS Latency Diagram," on page 14.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Figure 6, "CAS Latency
Table," on page 13, indicates the operating frequencies at which each CAS latency set-
ting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Figure 4: Mode Register Definition Diagram
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register (Mx)
0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 Burst Type
0 Sequential
1 Interleaved
M6 M5 M4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
M12 M11 M10 M9 M8 M7
0 0 0 0 00
0 0 0 0 10
- - - - --
M6-M0
Valid
Valid
-
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.

12 Page





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