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MT18VDDF6472 Schematic ( PDF Datasheet ) - Micron

Teilenummer MT18VDDF6472
Beschreibung 512MB DDR SDRAM REGISTERED DIMM
Hersteller Micron
Logo Micron Logo 




Gesamt 30 Seiten
MT18VDDF6472 Datasheet, Funktion
DDR SDRAM
REGISTERED DIMM
512MB, 1GB (x72, ECC, SR) PC3200
184-PIN DDR SDRAM RDIMM
MT18VDDF6472 – 512MB
MT18VDDF12872 – 1GB
For the latest data sheet, please refer to the MicronWeb
site: www.micron.com/products/modules
Features
• 184-pin, dual in-line memory module (DIMM)
• Fast data transfer rates: PC3200
• Utilizes 400 MT/s DDR SDRAM components
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Supports ECC error detection and correction
• 512MB (64 Meg x 72) and 1GB (128 Meg x 72)
• VDD = VDDQ = +2.6V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh modes
• 7.8125µs maximum average periodic refresh
interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
Figure 1: 184-Pin DIMM (MO-206)
Low-Profile 1.125in. (28.58mm)
Very Low Profile 0.72in. (18.29mm)
OPTIONS
• Operating Temperature Range
Commercial (0°C TA +70°C)
• Package
184-pin DIMM (standard)
184-pin DIMM (lead-free)1
• Memory Clock, Speed, CAS Latency2
5ns (200 MHz), 400 MT/s, CL = 3
• PCB
1.125in (28.58mm)
MARKING
none
G
Y
-40B
NOTE: 1. Contact Micron for availability of products.
2. CL = CAS latency; registered Mode adds one
clock cycle to CL.
Table 1: Address Table
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (64 Meg x 4)
2K (A0–A9, A11)
1 (S0#)
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (128 Meg x 4)
4K (A0–A9, A11, A12)
1 (S0#)
1pdf: 09005aef80f6b913, source: 09005aef80f6b41c
DDAF18C64_128x72G.fm - Rev. C 9/04 EN
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.






MT18VDDF6472 Datasheet, Funktion
512MB, 1GB (x72, ECC, SR) PC3200
184-PIN DDR SDRAM RDIMM
Figure 3: Functional Block Diagram – Low-Profile PCB
VSS
RS0#
DQS0
DQS9
DQS CS# DM
DQ0 DQ
DQ1 DQ U1
DQ2 DQ
DQ3 DQ
DQS CS# DM
DQ4 DQ
DQ5 DQ U24
DQ6 DQ
DQ7 DQ
DQS1
DQS10
DQ8
DQ9
DQ10
DQ11
DQS CS# DM
DQ
DQ U2
DQ
DQ
DQ12
DQ13
DQ14
DQ15
DQS CS# DM
DQ
DQ U23
DQ
DQ
DQS2
DQS11
DQ16
DQ17
DQ18
DQ19
DQS3
DQS CS# DM
DQ
DQ U3
DQ
DQ
DQ20
DQ21
DQ22
DQ23
DQS12
DQS CS# DM
DQ
DQ U22
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQS4
DQS CS# DM
DQ
DQ U4
DQ
DQ
DQ28
DQ29
DQ30
DQ31
DQS13
DQS CS# DM
DQ
DQ U21
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQS5
DQS CS# DM
DQ
DQ U8
DQ
DQ
DQ36
DQ37
DQ38
DQ39
DQS14
DQS CS# DM
DQ
DQ U18
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQS6
DQS CS# DM
DQ
DQ U9
DQ
DQ
DQ44
DQ45
DQ46
DQ47
DQS15
DQS CS# DM
DQ
DQ U17
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQS7
DQS CS# DM
DQ
DQ U10
DQ
DQ
DQ52
DQ53
DQ54
DQ55
DQS16
DQS CS# DM
DQ
DQ U16
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQS8
DQS CS# DM
DQ
DQ U11
DQ
DQ
DQ60
DQ61
DQ62
DQ63
DQS17
DQS CS# DM
DQ
DQ U15
DQ
DQ
S0?#
BA0, BA1
A0-A12
RAS#
CAS#
CKE0
WE#
CK
CK#
U6, U19
R
E
G
I
S
T
E
R
S
DQS CS# DM
CB0 DQ
CB1 DQ U5
CB2 DQ
CB3 DQ
DQS CS# DM
CB4 DQ
CB5 DQ U20
CB6 DQ
CB7 DQ
RS0#: DDR SDRAMs
RBA0, RBA1: DDR SDRAMs
RA0-RA12: DDR SDRAMs
RRAS#: DDR SDRAMs
RCAS#: DDR SDRAMs
RCKE0: DDR SDRAMs
RWE#: DDR SDRAMs
SCL
WP
VDD
RESET#
CK0
CK0#
120
VDD
PLL
U7
1K
SERIAL PD
U12
A0 A1 A2
SA0 SA1 SA2
VDDSPD
SDA
VDDQ
VDD
VREF
VSS
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
REGISTER X 2
SPD/EEPROM
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
NOTE:
1. All resistor values are 22unless otherwise specified.
2. Per industry standard, Micron utilizes various component speed
grades as referenced in the Module Part Numbering Guide at
www.micron.com/numberguide.
Standard modules use the following DDR SDRAM devices:
MT46V64M4FG (512MB); MT46V128M4FG (1GB)
Lead-free modules use the following DDR SDRAM devices:
MT46V64M4BG (512MB); MT46V128M4BG (1GB)
pdf: 09005aef80f6b913, source: 09005aef80f6b41c
DDAF18C64_128x72G.fm - Rev. C 9/04 EN
6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.

6 Page









MT18VDDF6472 pdf, datenblatt
512MB, 1GB (x72, ECC, SR) PC3200
184-PIN DDR SDRAM RDIMM
Commands
Table 8, Commands Truth Table, and Table 9, DM
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
of commands and operations, refer to the 256Mb or
512Mb DDR SDRAM component data sheet.
Table 8: Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NAME (FUNCTION)
CS# RAS# CAS# WE# ADDR
DESELECT (NOP)
HX
XX
X
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
LH
LL
LH
HH
X
H H Bank/Row
L H Bank/Col
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
LH
LH
LL
L L Bank/Col
HL
X
H L Code
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
L
L
L
L
LH
X
L L Op-Code
NOTES
1
1
2
3
3
4
5
6, 7
8
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0BA1 provide device bank address and A0A12 provide row address.
3. BA0BA1 provide device bank address; A0A9, A11 (512MB) or A0–A9, A11, A12 (1GB) provide column address; A10
HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0
BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
= 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0A12 provide the op-code
to be written to the selected mode register.
Table 9: DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
WRITE Enable
WRITE Inhibit
DM DQS
L Valid
HX
pdf: 09005aef80f6b913, source: 09005aef80f6b41c
DDAF18C64_128x72G.fm - Rev. C 9/04 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.

12 Page





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