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HCPL-063L Schematic ( PDF Datasheet ) - Avago

Teilenummer HCPL-063L
Beschreibung High Speed LVTTL Compatible 3.3 V Optocouplers
Hersteller Avago
Logo Avago Logo 




Gesamt 19 Seiten
HCPL-063L Datasheet, Funktion
HCPL-260L/060L/263L/063L
High Speed LVTTL Compatible 3.3 V Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
The HCPL-260L/060L/263L/063L are optically coupled
gates that combine a GaAsP light emitting diode and
an integrated high gain photo detector. An enable in-
put allows the detector to be strobed. The output of
the detector IC is an open collector Schottky-clamped
transistor. The internal shield provides a guaranteed
common mode transient immunity specification of
15 kV/µs at 3.3V.
This unique design provides maximum AC and DC circuit
isolation while achieving LVTTL/LVCMOS compati-bili-
ty. The optocoupler AC and DC operational parameters
are guaranteed from –40 °C to +85 °C allowing trouble-
free system performance.
These optocouplers are suitable for high speed logic
interfacing, input/output buffering, as line receivers in
environments that conventional line receivers cannot
tolerate and are recommended for use in extremely high
ground or induced noise environments.
Functional Diagram
HCPL-260L/060L
HCPL-263L/063L
NC 1
8 VCC ANODE 1 1
8 VCC
ANODE 2
7 VE CATHODE 1 2
7 VO1
CATHODE 3
6 VO CATHODE 2 3
6 VO2
NC 4 SHIELD
5 GND
Truth Table
(Positive Logic)
LED Enable Output
ON H
L
OFF H
H
ON L
H
OFF L
H
ON NC L
OFF NC H
ANODE 2 4
SHIELD
5 GND
Truth Table
(Positive Logic)
LED Output
ON L
OFF H
Features
3.3V/5V Dual Supply Voltages
Low power consumption
15 kV/µs minimum Common Mode Rejection (CMR) at
VCM = 1000 V
High speed: 15 MBd typical
LVTTL/LVCMOS compatible
Low input current capability: 5 mA
Guaranteed AC and DC performance over tempera-
ture: –40 °C to +85 °C
Available in 8-pin DIP, SOIC-8
Strobable output (single channel products only)
Safety approvals: UL, CSA, IEC/EN/DIN EN 60747-5-5
Applications
Isolated line receiver
Computer-peripheral interfaces
Microprocessor system interfaces
Digital isolation for A/D, D/A conversion
Switching power supply
Instrument input/output isolation
Ground loop elimination
Pulse transformer replacement
Field buses
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.






HCPL-063L Datasheet, Funktion
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics*
Description
Symbol
PDIP Option 060 SO-8 Option 060 Unit
Installation classification per DIN VDE 0110, Table 1
for rated mains voltage 150 Vrms
for rated mains voltage 300 Vrms
for rated mains voltage 600 Vrms
I – IV I – IV
I – IV I – IV
I – III I – III
Climatic Classification
40/85/21
40/85/21
Pollution Degree (DIN VDE 0110/39)
22
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm=1 sec,
Partial discharge < 5 pC
VIORM
VPR
630
1181
567
1063
Vpeak
Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec, Partial
discharge < 5 pC
VPR
1008
907
Vpeak
Highest Allowable Overvoltage
(Transient Overvoltage tini = 60 sec)
Safety-limiting values
– maximum values allowed in the event of a failure.
VIOTM
6000
6000
Vpeak
Case Temperature
TS 175
150 °C
Input Current
IS, INPUT
230
150 mA
Output Power
PS, OUTPUT
600
600 mW
Insulation Resistance at TS, VIO = 500 V
RS 109
109
W
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-5, for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Thermal Derating Curve Figures
800 HCPL-060L/HCPL-063L
700 PISS((mmAW) )
600
500
400
300
200
100
0 0 25 50 75 100 125 150 175 200
TS – CASE TEMPERATURE – °C
800 HCPL-260L/HCPL-263L
700 PISS((mmAW) )
600
500
400
300
200
100
0 0 25 50 75 100 125 150 175 200
TS – CASE TEMPERATURE – °C
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HCPL-063L pdf, datenblatt
Package Characteristics
All Typicals at TA = 25 °C.
Parameter
Sym. Package
Min. Typ. Max. Units Test Conditions
Fig. Note
Input-Output II-O* Single 8-Pin DIP 1 µA 45% RH, t = 5 s,
Insulation Single SO-8 VI-O = 3 kV DC, TA = 25 °C
16, 17
Input-Output VISO 8-Pin DIP, SO-8
3750
Vrms RH ≤ 50%, t = 1 min,
Momentary TA = 25 °C
Withstand
Voltage**
16, 17
Input-Output RI-O
Resistance
8-Pin, SO-8
1012
VI-O =500 Vdc
1, 16, 19
Input-Output CI-O
Capacitance
8-Pin DIP, SO-8
0.6
pF f = 1 MHz, TA = 25 °C
1, 16, 19
Input-Input II-I
Dual Channel
0.005
µA RH ≤ 45%, t = 5 s,
Insulation VI-I = 500 V
Leakage
20
Current
Resistance RI-I
(Input-Input)
Dual Channel
1011
20
Capacitance CI-I
(Input-Input)
Dual 8-Pin Dip
Dual SO-8
0.03
0.25
pG f = 1 MHz
20
*The JEDEC Registration specifies 0 °C to +70 °C. Avago specifies –40 °C to +85 °C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable), your equip-
ment level safety specification or Avago Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 15 mA.
4. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge
of the output pulse.
7. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge
of the output pulse.
8. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test
conditions.
9. See test circuit for measurement details.
10. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the
rising edge of the output pulse.
11. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the
falling edge of the output pulse.
12. CMH is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state
(i.e., Vo > 2.0 V).
13. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., Vo < 0.8 V).
14. For sinusoidal voltages, (|dVCM | / dt)max = πfCMVCM (p-p).
15. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved
CMR performance. For single channel products only. See application information provided.
16. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 Vrms for one second (leakage
detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/
EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable.
18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for one second (leakage
detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/
EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable.
19. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.
20. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.
12

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