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PDF LS013B7DH03 Data sheet ( Hoja de datos )

Número de pieza LS013B7DH03
Descripción Application Information for LCD Module
Fabricantes Sharp 
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LCD Module Application Information
LS013B7DH03
Application Information for Sharp’s LS013B7DH03 Memory LCD
Sharp Microelectronics of the Americas
INTRODUCTION
This Application Note provides additional design
assistance for Sharp’s LS013B7DH03 Memory LCD.
This module is a transflective, monolithic active-matrix
liquid crystal module utilizing Sharp’s CG-silicon thin-
film transistor process. Operating from a single 3 V
supply, it offers high performance and power efficiency
for compact display applications, with a serial interface
for simple integration.
Subjects covered will be:
• Mechanical Specifications, including dimension
drawings and connector specifications
• Absolute Maximum Ratings
• Optical Specifications, including view angles, reflec-
tivity, contrast, and risetime
• Electrical Characteristics, including interfacing and
signal timing information
• Design Notes
• Manufacturing Information, including handling and
storage
• Reliability Information
This Note is based on Sharp’s document number
LCP-2111042 and is designed to provide supplemen-
tary information for the Specifications for this part.
Always refer to the latest Specifications when
designing with these devices.
FEATURES
• Transflective monochrome panel
• Accepts a separate backlight for low-ambient situa-
tions
• Normally White
• Square aspect ratio (1:1)
• 1.28-inch screen with 128 × 128 resolution
• 3-wire serial interface
• Screen data is arbitrarily renewable by line
• Built-in, 1-bit internal memory in each pixel
• Super low power consumption TFT panel
• RoHS compliant
Application Information
1

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LS013B7DH03 pdf
LS013B7DH03 Application Information
LCD Modules
Coated Surface
(Optical Diffusion Treatment)
Normal Line
Photo Detector
(with Luminosity Correction System)
Beam
(Via Optical Fiber)
Diffused
Light
Diffused
Light
LCD Module
Center of Display
Figure 2. Setup for Contrast, Reflection Ratio, and Chromaticity
LS013B7DH03-25
ELECTRICAL SPECIFICATIONS
Here are the Recommended Operating Conditions
for this module, with VSS (GND) = 0 V and Ta = 25°C.
PARAMETER
Driver Supply Voltage
Input Signal Voltage
HIGH
LOW
Power Consumption 1
Power Consumption 2
SYMBOL
VDD
VINH
VINL
IVDD1
IVDD2
MIN.
2.7
VDD-0.1
VSS
TYP.
3.0
NOTES:
1. Applies to SCLK, SI, SCS, DISP, EXTCOMIN.
2. All-black display, no image updating.
SCS = SCLK = SI = L, EXTCOMIN = 60 Hz
3. 1-dot-wide vertical stripes, continuous image updating, SCLK = 1.1MHz, EXTCOMIN= 60 Hz
MAX.
3.3
VDD
VSS+0.1
20
340
UNIT
V
V
V
µA
µA
NOTES
1
2
3
Application Information
5

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LS013B7DH03 arduino
LS013B7DH03 Application Information
LCD Modules
Dynamic Mode
For software commands, see the Programming
Sharp’s Memory LCDs application note.
MULTIPLE LINE WRITE
Dynamic Mode assumes the updating of at least one
line in the display. During the Data Write period, data is
stored in the panel’s binary latch. During Data Transfer,
the data from the latch is written to the panel memory,
line-by-line. During the write to panel memory, data for
the next line is latched.
Dynamic Mode is entered by sending M0 = H and
M2 = L.
Figure 6 shows an example of writing multiple lines.
SINGLE LINE WRITE
Writing a single line of data is much the same as
writing multiple lines. During the Data Write period,
data is stored in the panel’s binary latch. During Data
Transfer, the data from the latch is written to the panel
memory, line-by-line. During the write to panel mem-
ory, data for the next line is latched.
Single Line Write requires the panel to be in
Dynamic Mode.
Dynamic Mode is entered the same way, by sending
M0 = H and M2 = L.
Figure 7 shows an example of writing a single line.
twSCSH
SCS
tsSCS
SI M0 M1 M2 DMY DMY DMY DMY DMY CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 D1 D2 D3 D4
tsSI
thSI
twSCLKL
twSCLKH
D125 D126 D127 D128 DON’T CARE CA0 CA1
CA6 CA7 D1 D2
SCLK
Mode Selection Period
(3ck + 5ckDMY)
Column address select period
(8ck)
CA1
Data Write Period
(128ck)
Data Transfer Period
(8ck(Dummy) + 8ck(address) = 16ck)
CA2
Data Write Period
(128ck)
twSCSH
twSCSL
D127 D128 DON’T CARE CA0 CA1 CA2
CA5 CA6 CA7 D1 D2
D127 D128
DUMMY DATA (don’t care)
thSCS
Column address select period
(8ck(Dummy) + 8ck(address) + 1ck(Dummy) = 16ck)
CA(n-1)th line
CA(n)th line
Data Writing Period
(128ck)
Data Transfer Period
(16ck)
Figure 6. Dynamic Mode Timing Diagram, Writing Multiple Lines
LS013B7DH03-18
twSCSH
SCS
tsSCS
SI M0 M1 M2 DMY DMY DMY DMY DMY CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 D1 D2 D3 D4
SCLK
tsSI
thSI
twSCLKL
twSCLKH
thSCS
D125 D126 D127 D128 DON’T CARE
twSCSL
Mode selection period (3ck+5ckDMY)
Column address select period (8ck)
Data writing period (128ck)
Data transfer period (16ck)
Figure 7. Dynamic Mode Timing Diagram, Writing a Single Line
LS013B7DH03-17
Application Information
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