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PDF LS010B7DH01 Data sheet ( Hoja de datos )
| Número de pieza | LS010B7DH01 | |
| Descripción | LCD Module | |
| Fabricantes | Sharp | |
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PREPARED BY: DATE
T. Wakai : 3 Dec. 2010
APPROVED BY: DATE
Y. Hataguchi : 3 Dec. 2010
LIQUID CRYSTAL DISPLAY GROUP
SHARP CORPORATION
SPECIFICATION
SPEC No.
LCP-2110042B
FILE No.
ISSUE
3 Dec. 2010
PAGE
Pages 27
APPLICABLE DIVISION
ENGINEERING DEPARTMENT I
LCD DIVISION II
LCD GROUP
DEVICE SPECIFICATION for
TFT LCD Module
Model No.
LS010B7DH01
CUSTOMER'S APPROVAL
DATE
BY
PRESENTED
BY
FUMIO KINOSHITA
DEPARTMENT GENERAL MANAGER
ENGINEERING DEPARTMENT I
LCD DIVISION II
LCD GROUP
SHARP CORPORATION
1 page  
LCP-2110042B-4
4. Input terminal names and functions
4-1. LCD-FPC
Table 2
#
1
2
3
4
5
6
7
8
9
10
symbol
SCLK
SI
SCS
EXTCOMIN
DISP
VDDA
VDD
EXTMODE
VSS
VSSA
I/O
I
I
I
I
I
-
-
I
-
-
Function
Serial clock signal
Serial data input signal
Chip select signal
External COM inversion signal input (H: enable)
Display on/off signal
Power supply (Analog)
Power supply (Digital)
COM inversion select terminal
GND (Digital)
GND (Analog)
Remark
Note 4-1
Note 4-2
[Note 4-1] The display on/off signal is only for display. Data memory will be saved also at the time of on/off.
”H”: data memory will be displayed.
”L”: white color will be displayed and data memory will be saved.
[Note 4-2] ”H”: enable EXTCOMIN signal, connect to VDD.
”L”: enable serial input flag, connect to VSS.
4-2. Recommended circuit
COM signal serial input
EXTMODE=”L”
SCLK
SI
SCS
EXTCOMIN
DISP
VDDA
VDD
EXTMODE
VSS
VSSA
Figure 1
COM signal serial input
EXTMODE=”H”
SCLK
SI
SCS
EXTCOMIN
DISP
VDDA
VDD
EXTMODE
VSS
VSSA
4-3. External circuit example
C1 C2 C3
C1,C2: 0.1uF/B/10V
C3: 1uF/B/10V
1 SCLK
2 SI
3 SCS
4 EXTCOMIN
5 DISP
6 VDDA
7 VDD
8 EXTMODE
9 VSS
10 VSSA
Figure 2
5 Page 
6-4. Input signal timing chart
Table 6
M0
H
L
L
H
M2 Mode
L
1)Data update mode (1 line)
2)Data Update Mode (Multiple lines)
L 3)Display Mode
H 4)All Clear Mode
H ignore
1) Data update mode (1 line)
Updates data of only one specified line (M0=“H”、M2＝“L”)
LCP-2110042B-10
twSCSH
SCS
tsSCS
SI
SCLK
M0 M1 M2 DMY DMY DMY DMY DMY AG0 AG1 AG2 AG3 AG4 AG5 AG6 AG7 D1 D2 D3 D4
tsSI thSI
twSCLKL twSCLKH
Mode select period
(3ck+5ckDMY)
Gate line address select period
(8ck)
Date write period
(128ck)
D125D126D127D128
Figure 6
DUMMY DATA(don't care)
Date transfer period
(16ck)
thSCS
M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)
When “L”, display mode (maintain memory internal data).
M1: Frame inversion flag
When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.
When EXTMODE=”H”, it can be “H” or “L”.
M2: All clear flag
Refer to 6-5-4) All Clear Mode to execute clear.
DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)
*Data write period
Data is being stored in 1st latch block of binary driver on panel.
*Data transfer period
Data written in 1st latch is being transferred (written) to pixel internal memory circuit.
*For gate line address setting, refer to 6-6) Input Signal and Display.
*M1: Frame inversion flag is enabled when EXTMODE=”L”.
*When SCS becomes “L”, M0 and M2 are cleared.
twSCSL
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