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Teilenummer | LQ057Q3DC03 |
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Beschreibung | LCD Module | |
Hersteller | Sharp | |
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Gesamt 21 Seiten APREPARED BY : DATE
APPROVED BY : DATE
DISPLAY DEVICE BUSINESS GROUP
SHARP CORPORATION
SPEC No. LD-26X14A
FILE No.
ISSUE : Oct. 28. 2014
PAGE : 21pages
APPLICABLE DIVISION
DISPLAY DEVICE BUSINESS
DIVISION
Revised: -
CUSTOMER'S APPROVAL
DATE
BY
PRESENTED
BY
T.Ohnishi
Department General Manager
Development Dept.
DISPLAY DEVICE UNIT
DISPLAY DEVICE BUSINESS DIVISION
SHARP CORPORATION
LD-26X14A-4
4 Input Signal Assignment
4-1. TFT-LCD Panel driving section
CN1 Using connector : FH12-33S-0.5SH(55) (HIROSE ELECTRIC CO., LTD.) Terminal:Gold plated
Table 4.1
Pin No.
Symbol
Function
Remark
1 GND
GND
2 CK
Dot-clock signal
3 HSYNC
Horizontal synchronous signal
Negative
4 VSYNC
Vertical synchronous signal
Negative
5 GND
GND
6 R0
RED data signal(LSB)
7 R1
RED data signal
8 R2
RED data signal
9 R3
RED data signal
10 R4
RED data signal
11 R5
RED data signal(MSB)
12 GND
GND
13 G0
GREEN data signal(LSB)
14 G1
GREEN data signal
15 G2
GREEN data signal
16 G3
GREEN data signal
17 G4
GREEN data signal
18 G5
GREEN data signal(MSB)
19 GND
GND
20 B0
BLUE data signal(LSB)
21 B1
BLUE data signal
22 B2
BLUE data signal
23 B3
BLUE data signal
24 B4
BLUE data signal
25 B5
BLUE data signal(MSB)
26 GND
GND
27 ENAB
Data enable signal (signal to settle the horizontal display position)
Positive
28 VCC
+3.3V power supply
29 VCC
+3.3V power supply
30
RL/UD
Selection signal for horizontal/vertical scanning direction
(“L” : Normally , “H” : Right-and-Left reversal/Up-and-Down reversal)
[Note4-2]
31 NC
No Connect
32 SHUT
No Connect(SHUT)(Please be sure to connect 32pin with GND)
33 GND
GND
[Note 4-1] Please use a compliant FFC/FPC with the input connector.
The terminal of FFC/FPC is recommended gold plated
(The whisker generation between a FPC and a connector and performance degradation caused by whisker is not
covered under warranty)
[Note 4-2]
RL/UD=L
RL/UD=H
6 Page LD-26X14A-10
Horizontal sync signal
(Hsync)
THp
0.9Vcc
0.1Vcc
0.1Vcc
THc
TH
Tc
Tch
Tcl
0.1Vcc
Clock signal
(CK)
Data(R0~5、
G0~5、B0~5)
Data Enable signal
(ENAB)
0.1Vcc
C1* C49* C50* C51*
(Number of clock count)
Horizintal invalid data period
D1 D2
The 0.9Vcc
Tes
D3 D4
Tds Tdh
Number of Horizontal data
D5 0.9Vcc D318 D319 D320
THd
Horizontal invalid data period
Tep
0.1Vcc
Vertical Sync signal
(Vsync)
0.1Vcc
TVh
TVp
0.9Vcc
TV
0.1Vcc
Horizontal sync signal
(Hsync)
Data(R0~5、
G0~5、B0~5)
0.9Vcc
Line1
Line2
TVb
Vertical invalid data period
Line7
(Number of Vertical count)
TVd
DH1 DH2 DH3
Fig 2. Input signal waveforms
DH239 DH240
Vertical invalid data period
12 Page | ||
Seiten | Gesamt 21 Seiten | |
PDF Download | [ LQ057Q3DC03 Schematic.PDF ] |
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