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XS1-L01A-LQ64 Schematic ( PDF Datasheet ) - Xmos

Teilenummer XS1-L01A-LQ64
Beschreibung MCU 32BIT 8KB OTP
Hersteller Xmos
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Gesamt 23 Seiten
XS1-L01A-LQ64 Datasheet, Funktion
XS1-L01A-LQ64 Datasheet
2012/10/15
XMOS © 2012, All Rights Reserved
Document Number: X1135,






XS1-L01A-LQ64 Datasheet, Funktion
XS1-L01A-LQ64 Datasheet
4 Block Diagram
X0D00
X0D01 ¶ ·
X0D02 ¶ ·
X0D03 ¶ ·
X0D04 ¶ ·
X0D05 ¶ ·
X0D06 ¶ ·
X0D07 ¶ ·
X0D08 ¶ ·
X0D09 ¶ ·
X0D10 ¶ ·
X0D11
X0D12
X0D13 ¶ ·
X0D14 ¶ ·
X0D15 ¶ ·
X0D16 ¶ ·
X0D17 ¶ ·
X0D18 ¶ ·
X0D19 ¶ ·
X0D20 ¶ ·
X0D21 ¶ ·
X0D22 ¶ ·
X0D23
X0D24
X0D25
X0D26
X0D27
X0D32
X0D33
X0D34
X0D35
X0D36
X0D37
X0D38
X0D39
TDI
TDO
TCK
TMS
TRST_N
DEBUG_N
PLL_AVDD
PLL_AGND
CLK
RST_N
MODE[3:0]
· 1A
1B
1C
· 1D
· 1E
1F
1G
· 1H
· 1I
· 1J
·
·
·
·
· 1K
· 1L
· 1M
· 1N
· 1O
· 1P
6 Clock Blocks
10 Timers
4 Locks
7 Synchronizers
PLL
VDD
VDDIO
GND
X0
Core 0
Core 1
Core 2
Core 3
Core 4
Core 5
Core 6
Core 7
64KB SRAM
JTAG
Boot ROM
Security Register
8KB OTP
X1135,
5

6 Page









XS1-L01A-LQ64 pdf, datenblatt
XS1-L01A-LQ64 Datasheet
11
This pin should have an external pull up of 4K7-47K Ω or left not connected in
single core applications.
The JTAG device identification register can be read by using the IDCODE instruction.
Its contents are specified in Figure 6.
Figure 6:
IDCODE
return value
Bit31
Device Identification Register
Bit0
Version
Part Number
Manufacturer Identity
1
00000000000000000010011000110011
00002633
The JTAG usercode register can be read by using the USERCODE instruction. Its
contents are specified in Figure 7. The OTP User ID field is read from bits [22:31]
of the security register (all zero on unprogrammed devices).
Figure 7:
USERCODE
return value
Bit31
Usercode Register
Bit0
OTP User ID
Unused
Silicon Revision
00000000000000101000000000000000
00028000
5.10 Power Supplies
The device has the following types of power supply pins:
· VDD pins for the xCORE Tile tile
· VDDIO pins for the I/O lines
· PLL_AVDD pins for the PLL
Several pins of each type are provided to minimize the effect of inductance within
the package, all of which must be connected. The power supplies must be brought
up monotonically and input voltages must not exceed specification at any time.
The VDD supply must ramp from 0 V to its final value within 10 ms to ensure
correct startup.
The VDDIO supply must ramp to its final value before VDD reaches 0.4 V.
The PLL_AVDD supply should be separated from the other noisier supplies on
the board. The PLL requires a very clean power supply, and a low pass filter (for
example, a 4.7 Ω resistor and 100 nF multi-layer ceramic capacitor) is recommended
on this pin.
The following ground pins are provided:
· PLL_AGND for PLL_AVDD
· GND for all other supplies
All ground pins must be connected directly to the board ground.
X1135,

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