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MK20DN32VMP5 Schematic ( PDF Datasheet ) - Freescale Semiconductor

Teilenummer MK20DN32VMP5
Beschreibung ARM CORTEX MCU
Hersteller Freescale Semiconductor
Logo Freescale Semiconductor Logo 




Gesamt 30 Seiten
MK20DN32VMP5 Datasheet, Funktion
K20 Sub-Family Reference Manual
Supports: MK20DN32VLH5, MK20DX32VLH5, MK20DN64VLH5,
MK20DX64VLH5, MK20DN128VLH5, MK20DX128VLH5,
MK20DN32VMP5, MK20DX32VMP5, MK20DN64VMP5,
MK20DX64VMP5, MK20DN128VMP5, MK20DX128VMP5
Document Number: K20P64M50SF0RM
Rev. 2, Feb 2012






MK20DN32VMP5 Datasheet, Funktion
Section Number
Title
Page
4.2 System memory map.....................................................................................................................................................131
4.2.1 Aliased bit-band regions..............................................................................................................................132
4.3 Flash Memory Map.......................................................................................................................................................133
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................134
4.4 SRAM memory map.....................................................................................................................................................134
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................135
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................135
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................139
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................141
5.2 Programming model......................................................................................................................................................141
5.3 High-Level device clocking diagram............................................................................................................................141
5.4 Clock definitions...........................................................................................................................................................142
5.4.1 Device clock summary.................................................................................................................................143
5.5 Internal clocking requirements.....................................................................................................................................144
5.5.1 Clock divider values after reset....................................................................................................................145
5.5.2 VLPR mode clocking...................................................................................................................................145
5.6 Clock Gating.................................................................................................................................................................146
5.7 Module clocks...............................................................................................................................................................146
5.7.1 PMC 1-kHz LPO clock................................................................................................................................148
5.7.2 WDOG clocking..........................................................................................................................................148
5.7.3 Debug trace clock.........................................................................................................................................148
5.7.4 PORT digital filter clocking.........................................................................................................................149
5.7.5 LPTMR clocking..........................................................................................................................................149
5.7.6 USB FS OTG Controller clocking...............................................................................................................150
5.7.7 UART clocking............................................................................................................................................150
5.7.8 I2S/SAI clocking..........................................................................................................................................151
5.7.9 TSI clocking.................................................................................................................................................151
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
6 Freescale Semiconductor, Inc.

6 Page









MK20DN32VMP5 pdf, datenblatt
Section Number
Title
Page
15.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................282
15.4 I/O retention..................................................................................................................................................................283
15.5 Memory map and register descriptions.........................................................................................................................283
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................283
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................285
15.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................286
Chapter 16
Low-Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................289
16.1.1 Features........................................................................................................................................................289
16.1.2 Modes of operation......................................................................................................................................290
16.1.3 Block diagram..............................................................................................................................................291
16.2 LLWU signal descriptions............................................................................................................................................292
16.3 Memory map/register definition...................................................................................................................................293
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................294
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................295
16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................296
16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................297
16.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................298
16.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................300
16.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................301
16.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................303
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................305
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................306
16.3.11 LLWU Reset Enable register (LLWU_RST)...............................................................................................307
16.4 Functional description...................................................................................................................................................308
16.4.1 LLS mode.....................................................................................................................................................308
16.4.2 VLLS modes................................................................................................................................................308
16.4.3 Initialization.................................................................................................................................................309
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
12 Freescale Semiconductor, Inc.

12 Page





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