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MK10DN32VFM5 Schematic ( PDF Datasheet ) - Freescale Semiconductor

Teilenummer MK10DN32VFM5
Beschreibung Microcontroller
Hersteller Freescale Semiconductor
Logo Freescale Semiconductor Logo 




Gesamt 30 Seiten
MK10DN32VFM5 Datasheet, Funktion
K10 Sub-Family Reference Manual
Supports: MK10DN32VFM5, MK10DX32VFM5, MK10DN64VFM5,
MK10DX64VFM5, MK10DN128VFM5, MK10DX128VFM5
Document Number: K10P32M50SF0RM
Rev. 2, Feb 2012






MK10DN32VFM5 Datasheet, Funktion
Section Number
Title
Page
4.3 Flash Memory Map.......................................................................................................................................................125
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................126
4.4 SRAM memory map.....................................................................................................................................................126
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................127
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................127
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................131
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................133
5.2 Programming model......................................................................................................................................................133
5.3 High-Level device clocking diagram............................................................................................................................133
5.4 Clock definitions...........................................................................................................................................................134
5.4.1 Device clock summary.................................................................................................................................135
5.5 Internal clocking requirements.....................................................................................................................................136
5.5.1 Clock divider values after reset....................................................................................................................137
5.5.2 VLPR mode clocking...................................................................................................................................137
5.6 Clock Gating.................................................................................................................................................................138
5.7 Module clocks...............................................................................................................................................................138
5.7.1 PMC 1-kHz LPO clock................................................................................................................................139
5.7.2 WDOG clocking..........................................................................................................................................140
5.7.3 Debug trace clock.........................................................................................................................................140
5.7.4 PORT digital filter clocking.........................................................................................................................141
5.7.5 LPTMR clocking..........................................................................................................................................141
5.7.6 UART clocking............................................................................................................................................142
5.7.7 I2S/SAI clocking..........................................................................................................................................142
5.7.8 TSI clocking.................................................................................................................................................142
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................145
K10 Sub-Family Reference Manual, Rev. 2, Feb 2012
6 Freescale Semiconductor, Inc.

6 Page









MK10DN32VFM5 pdf, datenblatt
Section Number
Title
Page
15.5 Memory map and register descriptions.........................................................................................................................269
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................269
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................271
15.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................272
Chapter 16
Low-Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................275
16.1.1 Features........................................................................................................................................................275
16.1.2 Modes of operation......................................................................................................................................276
16.1.3 Block diagram..............................................................................................................................................277
16.2 LLWU signal descriptions............................................................................................................................................278
16.3 Memory map/register definition...................................................................................................................................279
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................280
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................281
16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................282
16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................283
16.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................284
16.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................286
16.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................287
16.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................289
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................291
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................292
16.3.11 LLWU Reset Enable register (LLWU_RST)...............................................................................................293
16.4 Functional description...................................................................................................................................................294
16.4.1 LLS mode.....................................................................................................................................................294
16.4.2 VLLS modes................................................................................................................................................294
16.4.3 Initialization.................................................................................................................................................295
K10 Sub-Family Reference Manual, Rev. 2, Feb 2012
12 Freescale Semiconductor, Inc.

12 Page





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