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HI-5046A-883 Schematic ( PDF Datasheet ) - Intersil

Teilenummer HI-5046A-883
Beschreibung DPDT CMOS Analog Switch
Hersteller Intersil
Logo Intersil Logo 




Gesamt 12 Seiten
HI-5046A-883 Datasheet, Funktion
DPDT CMOS Analog Switch
HI-5046A/883
This CMOS analog switch offers low-resistance switching
performance for analog voltages up to the supply rails and for
signal currents up to 70mA. “ON” resistance is low and stays
reasonably constant over the full range of operating signal
voltage and current. RON remains exceptionally constant for
input voltages between +5V and -5V and currents up to 50mA.
Switch impedance also changes very little over temperature,
particularly between 0°C and +75°C. RON is nominally 25
for the HI-5046A/883.
This device provides break-before-make switching and is TTL
and CMOS compatible for maximum application versatility.
Performance is further enhanced by Dielectric Isolation
processing which insures latch-free operation with very low
input and output leakage currents (0.8nA at +25°C). The
HI-5046A/883 also features very low power operation (1.5mW
at +25°C). The HI-5046A/883 is available in a 16 Ld CerDIP
package and is specified over the temperature range of -55°C
to +125°C.
Pin Configuration
HI1-5046/883
(16 LD CERDIP)
TOP VIEW
LOGIC “0” INPUT
D2 1
2
D1 3
S1 4
S4 5
D4 6
7
D3 8
16 S2
15 A
14 V-
13 VR
12 VL
11 V+
10
9 S3
NOTE: Unused pins may be internally connected. Ground all unused pins.
Ordering Information
PART NUMBER
PART
TEMP. RANGE
PKG.
MARKING
(°C) PACKAGE DWG. #
HI1-5046A/883 HI1-5046A/883 -55 to +125 16 Ld CerDIP F16.3
Features
• This Circuit is Processed in Accordance to MIL-STD-883 and
is Fully Conformant Under the Provisions of Paragraph 1.2.1.
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Low “On” Resistance . . . . . . . . . . . . . . 25(Typ), 50(Max)
• High Current Capability . . . . . . . . . . . . . . . . . . . . . 70mA (Max)
• Break-Before-Make Switching
- Turn-On Time. . . . . . . . . . . . . . . . . 370ns (Typ), 800ns (Max)
- Turn-Off Time . . . . . . . . . . . . . . . .280ns (Typ), 400ns (Max)
• No Latch Up
• Input MOS Gates are Protected from Electrostatic Discharge
• DTL, TTL, CMOS, PMOS Compatible
Applications
• High Frequency Analog
• Sample and Hold
• Digital Filters
• Operational Amplifier Gain Switching
Functional Diagram
LOGIC “1” INPUT
S1 4
S2 16
9
S3
S4 5
A 15
VL V+
12 11
3
1
8
6
D1
D2
D3
D4
13
VR
14
V-
TYPICAL SWITCH
S
A NP
D
NOTE: Source and Drain are arbitrarily depicted as Analog Input and
Output, respectively. They may be interchanged without affecting
performance.
May 3, 2012
FN8274.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1989, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.






HI-5046A-883 Datasheet, Funktion
HI-5046A/883
Test Characteristics (Continued)
720
660
600
540
480
420
360 tON
300 tOFF
240
180
120
60
2.4
3.0
3.6 4.2
4.8
DIGITAL “HIGH” (VAH)
FIGURE 11. SWITCHING TIMES FOR DIGITAL TRANSITION
720
660
600
540
480
420
360 tON
300
240 tOFF
180
120
60
0 0.5 1.0 1.5
DIGITAL “LOW” (VAL)
FIGURE 12. SWITCHING TIMES FOR NEGATIVE DIGITAL TRANSITION
Test Waveforms
5V 5V
INPUT
INPUT
OUTPUT
5V
100ns
Vertical Scale: Input = 5V/Div, (TTL; VAH = 5V, VAL = 0V)
Output = 5V/Div
Horizontal Scale: 100ns/Div
FIGURE 13.
OUTPUT
5V
100ns
Vertical Scale: Input = 5V/Div, (CMOS; VAH = 10V, VAL = 0V)
Output = 5V/Div
Horizontal Scale: 100ns/Div
FIGURE 14.
6 FN8274.0
May 3, 2012

6 Page









HI-5046A-883 pdf, datenblatt
HI-5046A/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
-A- -D-
E
-B-
bbb S C A - B S D S
c1 LEAD FINISH
BASE
METAL
(c)
b1
MM
(b)
SECTION A-A
BASE
PLANE
SEATING
PLANE
S1
b2
b
D
AA
e
Q
-C- A
L
eA/2
α
eA
c
ccc M C A - B S D S
aaa M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located ad-
jacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identi-
fication mark.
2. The maximum limits of lead dimensions b and c or M shall be measured
at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M ap-
plies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial
lead paddle. For this configuration dimension b3 replaces dimension
b2.
5. This dimension allows for off-center lid, meniscus, and glass overrun.
6. Dimension Q shall be measured from the seating plane to the base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN
MAX
MIN
MAX NOTES
A
- 0.200 - 5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
- 0.840
- 21.34
5
E
0.220
0.310
5.59
7.87
5
e 0.100 BSC
2.54 BSC
-
eA 0.300 BSC
7.62 BSC
-
eA/2 0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1 0.005 - 0.13
α 90o 105o 90o
-
105o
7
-
aaa
- 0.015 - 0.38
-
bbb - 0.030 - 0.76 -
ccc
- 0.010 - 0.25
-
M
-
0.0015
-
0.038
2, 3
N 16
16 8
Rev. 0 4/94
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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