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PDF AD4000 Data sheet ( Hoja de datos )
| Número de pieza | AD4000 | |
| Descripción | 2 MSPS Precision Pseudo Differential ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
16-Bit, 2 MSPS Precision
Pseudo Differential ADC
AD4000
FEATURES
Throughput: 2 MSPS maximum
INL: ±1.0 LSB maximum
Guaranteed 16-bit no missing codes
Low power
9.75 mW at 2 MSPS (VDD only)
70 µW at 10 kSPS, 14 mW at 2 MSPS (total)
SNR: 93 dB typical at 1 kHz, 90 dB typical at 100 kHz
THD: −115 dB typical at 1 kHz, −95 dB typical at 100 kHz
Ease of use features reduce system power and complexity
Input overvoltage clamp circuit
Reduced nonlinear input charge kickback
High-Z mode
Long acquisition phase
Input span compression
Fast conversion time allows low SPI clock rates
SPI-programmable modes, read/write capability, status word
Pseudo differential (single-ended) analog input range: 0 V to
VREF with VREF between 2.4 V to 5.1 V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
SAR architecture: no latency/pipeline delay
Guaranteed operation: −40°C to 125°C
Serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible
Ability to daisy-chain multiple ADCs and busy indicator
10-lead package: 3 mm × 3 mm LFCSP and 3 mm × 4.90 mm
MSOP
APPLICATIONS
Automatic test equipment
Machine automation
Medical equipment
Battery-powered equipment
Precision data acquisition systems
GENERAL DESCRIPTION
The AD4000 is a low noise, low power, high speed, 16-bit,
2 MSPS precision successive approximation register (SAR)
analog-to-digital converter (ADC). It incorporates ease of use
features that lower the signal chain power, reduce signal chain
complexity, and enable higher channel density. The high-Z mode,
coupled with a long acquisition phase, eliminates the need for a
dedicated high power, high speed ADC driver, thus broadening the
range of low power precision amplifiers that can drive this ADC
directly while still achieving optimum performance. The input span
compression feature enables the ADC driver amplifier and the
ADC to operate off common supply rails without the need for a
negative supply while preserving the full ADC code range. The low
serial peripheral interface (SPI) clock rate requirement reduces the
digital input/output power consumption, broadens processor
options, and simplifies the task of sending data across digital
isolation.
Operating from a 1.8 V supply, the AD4000 samples an analog
input (IN+) between 0 V to VREF with respect to a ground sense
(IN−) with VREF ranging from 2.4 V to 5.1 V. The AD4000
consumes only 14 mW at 2 MSPS with a minimum of 75 MHz
SCK rate in turbo mode and achieves ±1.0 LSB INL maximum,
no missing codes at 16 bits with 93 dB SNR. The reference voltage
is applied externally and can be set independently of the supply
voltage.
The SPI-compatible versatile serial interface features seven
different modes including the ability, using the SDI input, to
daisy-chain several ADCs on a single 3-wire bus and provides an
optional busy indicator. The AD4000 is compatible with 1.8 V,
2.5 V, 3 V, and 5 V logic, using the separate VIO supply.
The AD4000 is available in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +125°C. The device is
pin compatible with the 18-bit, 2 MSPS AD4003.
VREF
VREF/2
0
FUNCTIONAL BLOCK DIAGRAM
2.5V TO 5V
10µF
1.8V
REF
VDD
HIGH-Z AD4000
MODE
IN+
18-BIT
SAR ADC
IN–
CLAMP
SPAN
COMPRESSON
TURBO
MODE
SERIAL
INTERFACE
STATUS
BITS
VIO 1.8V TO 5V
SDI
SCK
SDO
CNV
3-WIRE OR 4-WIRE
SPI INTERFACE
(DAISY CHAIN, CS)
GND
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD4000
Data Sheet
Parameter
−3 dB Input Bandwidth
Aperture Delay
Aperture Jitter
REFERENCE
Voltage Range (VREF)
Current
OVERVOLTAGE CLAMP
IIN+/IIN−
VIN+/VIN− at Maximum IIN+/IIN−
VIN+/VIN− Clamp On/Off Threshold
Deactivation Time
REF Current at Maximum IIN+
DIGITAL INPUTS
Logic Levels
Input Low Voltage, VIL
Input High Voltage, VIH
Input Low Current, IIL
Input High Current, IIH
Input Pin Capacitance
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Output Low Voltage, VOL
Output High Voltage, VOH
POWER SUPPLIES
VDD
VIO
Standby Current
Power Dissipation
VDD Only
REF Only
VIO Only
Energy per Conversion
TEMPERATURE RANGE
Specified Performance
Test Conditions/Comments
2 MSPS, VREF = 5 V
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
VIN+ > VREF
VIO > 2.7 V
VIO ≤ 2.7 V
VIO > 2.7 V
VIO ≤ 2.7 V
ISINK = 500 µA
ISOURCE = −500 µA
VDD and VIO = 1.8 V, T = 25°C
VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V
10 kSPS, high-Z mode disabled
1 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
1 MSPS, high-Z mode enabled
2 MSPS, high-Z mode enabled
2 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
TMIN to TMAX
Min
Typ Max
Unit
10 MHz
1 ns
1 ps rms
2.4 5.1 V
0.75 mA
50 mA
50 mA
5.4 V
3.1 V
5.25 5.4
V
2.68 2.8
V
360 ns
100 µA
−0.3
−0.3
0.7 × VIO
0.8 × VIO
−1
−1
6
+0.3 × VIO
+0.2 × VIO
VIO + 0.3
VIO + 0.3
+1
+1
V
V
V
V
µA
µA
pF
Serial 16 bits, straight binary
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
V
V
1.71
1.8 1.89
V
1.71 5.5 V
1.6 µA
70
7
14 16
8
16 19
9.75
3.75
0.5
7
µW
mW
mW
mW
mW
mW
mW
mW
nJ/sample
−40
+125
°C
1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS.
2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
3 Transient response is the time required for the ADC to acquire a full scale input step to ±0.5 LSB accuracy.
4 The minimum and maximum values are guaranteed by characterization, not production tested.
5 See the 1/f noise plot in Figure 18.
Rev. 0 | Page 4 of 32
5 Page 
AD4000
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 1.8 V; VIO = 3.3 V; VREF = 5 V; T = 25°C, high-Z mode disabled, span compression disabled and turbo mode enabled
(fS = 2 MSPS), unless otherwise noted.
0.5
+125°C
0.4 +25°C
–40°C
0.3
0.2
0.1
0.20
0.15
0.10
0.05
00
–0.1
–0.2
–0.3
–0.4
–0.5
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE
Figure 5. INL vs. Code and Temperature, VREF = 5 V
–0.05
–0.10
–0.15
–0.20
0
+125°C
+25°C
–40°C
8192 16384 24576 32768 40960 49152 57344 65536
CODE
Figure 8. DNL vs. Code and Temperature, VREF = 5 V
0.3
+125°C
+25°C
0.2 –40°C
0.1
0
–0.1
–0.2
–0.3
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE
Figure 6. INL vs. Code and Temperature, VREF = 2.5 V
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0
+125°C
+25°C
–40°C
8192 16384 24576 32768 40960 49152 57344 65536
CODE
Figure 9. DNL vs. Code and Temperature, VREF = 2.5 V
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
0
SPAN COMPRESSION ENABLED
HIGH-Z ENABLED
8192 16384 24576 32768 40960 49152 57344 65536
CODE
Figure 7. INL vs. Code, High-Z and Span Compression Modes Enabled, VREF = 5 V
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0
SPAN COMPRESSION ENABLED
HIGH-Z ENABLED
8192 16384 24576 32768 40960 49152 57344 65536
CODE
Figure 10. DNL vs. Code, High-Z and Span Compression Modes Enabled, VREF = 5 V
Rev. 0 | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD4000.PDF ] | |
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