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TW5866 Schematic ( PDF Datasheet ) - Intersil

Teilenummer TW5866
Beschreibung 9D1 H.264 CODEC
Hersteller Intersil
Logo Intersil Logo 




Gesamt 30 Seiten
TW5866 Datasheet, Funktion
NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PARTS
TW2819, TW2809
9D1 H.264 CODEC with 8-Channel A/V Decoder
TW5866
TW5866 is a H.264 CODEC solution with integrated
8-channel analog A/V decoders. TW5866 supports up to 9D1
of H.264 video encoding, 8D1 of H.264 video decoding, or
4D1 H.264 full duplex codec. In addition, TW5866 supports
motion JPEG encoding and video preview through BT.656
interfaces and PCI interfaces. TW5866 can be used in low
cost H.264 hardware compression PCI card to support either
8-channel with a single chip, or 16-channel with two chips. It
can also work with two external TW2866 to support 16-CIF
H.264 compression. TW5866 can also be used in embedded
DVR applications as an AV front-end chip working with
display mux capable SOCs.
TW5866 integrates 8 A/V decoders. It takes 8 CVBS analog
inputs fed into eight internal high quality NTSC/PAL video
decoders. In addition, it has 2 digital BT.656 / 1120
interfaces, running up to 108/148.5 MHz, capable of
receiving up to 8 D1, 2 720P / 1080i / 1080p HD video
sources. When used as D1 input, the digital interface takes
multi-channel video signal from external video decoders,
such as TW2866 / TW2867. This allows the TW5866 to
support a total of 16 D1 video channels. All the SD / HD
video streams are fed into H.264 encoder, MJPEG encoder
for compression, and to PCI interface and digital 656 output
interface for preview purposes. The H.264 decoded stream
from the on-chip video decoder is fed through two BT.656 /
1120 playback interfaces to drive the external display
processors. The BT.656 playback interfaces runs up to 108
MHz and is capable of delivering multi-channel byte-
interleaving or field/frame interleaving format for total of 8
D1 playback channels.
TW5866 supports functions per channel, such as motion
detection, night detection, and blind detection engine for
channel alarm notification. It features triple scalers per
channel for each of the H.264 encode, MJPEG, and PCI
preview paths. Each of these scalers is independently
configurable. TW5866 also features per channel OSDs and
motion adaptive de-interlacer. TW5866 supports 8-channel
of motion adaptive 2D de-interlacers and 2D noise reduction.
TW5866 integrates a H.264 baseline level 3 compliant
encoder capable of performing up to either 9 D1 equivalent
video encoding (225 fps for PAL and 270 fps for NTSC), 8 D1
decoding, 17 channel G.726 ADPCM hardware audio encoder
with one channel for two way audio communication, and one
channel ADPCM audio decoding. The H.264 video encoder
supports dual-bitstream compression for both local storage
and network streams. It also features a motion JPEG encoder
for up to 25 frames per second shared among all video
channels.
TW5866 provides PCI interface for external CPU control and
bitstream upload. The PCI interface runs at 33 or 66 MHz The
external CPU can access the internal meta-data associated
with each H.264 channel for video analytic purposes.
Analog Video Decoder
8 CVBS analog inputs fed into 8 sets of video decoder
accept all NTSC(M/N/4.43) / PAL
(B/D/G/H/I/K/L/M/N/60) standards with auto detection
Integrated video analog anti-aliasing filters and 10-bit
CMOS ADCs for each video decoder
High performance adaptive 4H comb filters for all
NTSC/PAL standards
IF compensation filter for improvement of color
demodulation
Color Transient Improvement (CTI)
Automatic white peak control
Programmable hue, saturation, contrast, brightness and
sharpness
Proprietary fast video locking system for non-real-time
application
Noise Reduction to remove impulse noise
Digital Input Ports
BT.656
Two BT.656 ports at up to 108 MHz interfaced with 2
external TW2866s
Byte-interleaving supports 4 channels multiplexing with
each channel of interlaced D1 at 60/50 fps
BT.1120
Two BT.1120 ports to support external HD video sources
of 720P / 1080i / 1080p format at 74.25 / 148.5 MHz
One cascade input supporting cascade of multiple
TW5866 chips. This is pin shared with one playback port
Pre-processing
Per channel triple high performance down scalers of each
channel scale independently for H.264, JPEG and preview
output
Per channel motion detector with 16 X 12 cells
Per channel night / blind detections
Per channel noise reduction and de-interlacing to convert
Interlaced video into progressive before compression
Per channel OSD for information overlay
Single Box
1-bit per pixel text
2-bit per pixel text or mask
12-bit per pixel bitmap
FN8319.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
February 27, 2013
All other trademarks mentioned are the property of their respective owners.






TW5866 Datasheet, Funktion
TW5866
Table of Figures
Figure 1. TW5866 BLOCK DIAGRAM ....................................................................................................................................................................... 3
Figure 2. TW5866 8-CHANNEL PC CARD SOLUTION .............................................................................................................................................. 4
Figure 3. TW5866 16-CHANNEL DVR SOLUTION.................................................................................................................................................... 4
Figure 4. TW5866 BALL ARRANGEMENT (BOTTOM VIEW) .................................................................................................................................... 8
Figure 5. The Frequency Response of the Video Input Anti-alias Filter............................................................................................................... 19
Figure 6. The Characteristic of Decimation Filter ................................................................................................................................................. 19
Figure 7. The Characteristics of Luminance Notch Filter for NTSC and PAL ...................................................................................................... 21
Figure 8. THE CHARACTERISTICS OF CHROMINANCE BAND-PASS FILTER FOR NTSC / PAL............................................................................ 21
Figure 9 THE CHARACTERISTICS OF CHROMINANCE LOW-PASS FILTER CURVES............................................................................................. 22
Figure 10. The Characteristic of Luminance Peaking filter ................................................................................................................................. 23
Figure 11. Timing Diagram of ITU-R BT.656 Format ............................................................................................................................................ 24
Figure 12. Timing Diagram of 108MHz 4 Ch D1 Time-Division-Multiplexed Video data ................................................................................... 26
Figure 13. PIN OUTPUT TIMING OF 108MHZ 4 CH D1 TIME-DIVISION-MULTIPLEXED VIDEO DATA WITH 108MHZ CLOCK. ........................... 26
Figure 14. HD Interfaces for (a) Two HD Inputs / TWO HD Playback, (b) HD Cascade ...................................................................................... 28
Figure 15. Formed Interlaced D1 Picture as Byte-Interleaved Source of BT.656 Playback Port ...................................................................... 29
Figure 16. Formed progressive D1 Picture as Byte-Interleaved Source of BT.656 Playback Port.................................................................... 29
Figure 17. Interlaced D1 Field Interleaved: Type 0 (left) and Frame Interleaved: Type 1 (right) ...................................................................... 29
Figure 18. Interlaced CIF Field Interleaved: Type 2 (left) and Frame Interleaved: Type 3 (right) ...................................................................... 29
Figure 19. Half D1 Field Interleaved: type 6 ......................................................................................................................................................... 29
Figure 20. 4D1 Output format: Single Channel (Left), Quad Channel (Right), and 16 Channel (Bottom)....................................................... 30
Figure 21. 720P Output format: Single Channel (Left) and Quad Channel (Right) ............................................................................................ 30
Figure 22. 1080i Output format: Single Channel (Left) and Quad Channel (Right) ........................................................................................... 30
Figure 23. Two TW5866 Cascade to Support 1 Window of 4x D1 Resolution, 4 Windows in D1 or 16 Windows in Cif................................. 30
Figure 24. Two TW5866 Cascade to Support Single HD Windows or 4 Windows in ¼ HD............................................................................... 30
Figure 25. The Pre-Processing Module.................................................................................................................................................................. 31
Figure 26. Motion Mask and Detection Cells for D1 Case ................................................................................................................................... 33
Figure 27. The Relationship Between Current and Reference Field When md_reffld = “0” ............................................................................. 34
Figure 28. The Relationship Between Current and Reference Field When md_reffld = “1” ............................................................................. 34
Figure 29. H.264 Encoding Capture Path Channel Selection .............................................................................................................................. 36
Figure 30. MJPEG Encoding Capture Path Channel Selection............................................................................................................................. 38
Figure 31. PCI Preview Path Channel Selection ................................................................................................................................................... 39
Figure 32.5-channel Audio CODEC Units in TW2866 ........................................................................................................................................... 42
Figure 33. 10-channel Audio CODEC Units in TW5866 Consisting of Two 5-Channel AUDIO Codecs .............................................................. 43
Figure 34. Audio Decimation Filter Response ...................................................................................................................................................... 43
Figure 35. Timing Chart of Serial Audio Interface ................................................................................................................................................ 44
Figure 36. Timing Chart of Serial Audio Interface ................................................................................................................................................ 45
Figure 37. Cascade of Two TW5866 to Support 20 Channel Audio.................................................................................................................... 47
Figure 38. DDR2 Interface Clock timing .............................................................................................................................................................225
Figure 39. DDR2 INTERFACE OUTPUT TIMING ....................................................................................................................................................225
Figure 40. DDR2 Interface Input Timing .............................................................................................................................................................225
Figure 41. PCI Interface Timing Condition ..........................................................................................................................................................226
Figure 42. Video Interface Input Timing ..............................................................................................................................................................228
Figure 43. Video Interface Output Timing ...........................................................................................................................................................228
Figure 44. I2C Interface Timing Condition ...........................................................................................................................................................229
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TW5866 pdf, datenblatt
Digital Video Interface
TW5866
NAME
BALL #
(MSB FIRST FOR BUS
SIGNALS)
PV1_DATA[7:0]
H3, H2, H1, G3, G2,
G1, F2, F1
PV1_CLK
J1
PV2_DATA[7:0]
L3, L2, K3, K2, K1,
J4, J3, J2
PV2_CLK
L1
PB1_DATA[7:0]
B24, A25, B25, C25,
A26, B26, C26, D26
PB1_CLK
A24
PB2_DATA[7:0]
B21, A22, B22, C22,
D22, A23, B23, C23
PB2_CLK
A21
PB_HD2_Y_DATA[7:0]
D15, A16, B16, C16,
D16, A17, B17, A18
PB_HD2_C_DATA[7:0]
B18, C18, D18, A19,
B19, B20, C20, D20
PB_HD2_CLK
A20
HD2_Y_DATA[7:0]
HD2_C_DATA[7:0]
HD2_CLK
VD1_DATA[7:0]
VD1_CLK
VD2_DATA[7:0]
VD2_CLK
A11, B11, A12, B12,
C12, D12, B13, C13
D13, A14, B14, C14,
D14, A15, B15, C15
A13
B6, A7, B7, C7, D7,
B8, C8, D8
A6
A9, B9, C9, D9, A10,
B10, C10, D10
A8
TYPE
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I
I
I
I
I
I
I
DESCRIPTION
Video data of preview output port 0 in BT. 656
Clock of preview output port 0
Video data of preview output port 1 in BT. 656
Clock of preview output port 1
Video playback SD data output port 1 in BT. 656 /
Video playback HD data output bit C[7:0] of BT.1120 port 1
Clock of playback output of SD BT. 656 port 1 / HD BT. 1120 port 1
Video playback SD data output port 2 in BT. 656 /
Video playback HD data output bit Y[7:0] of BT.1120 port 1
Clock of playback output of BT. 656 port 2
HD playback port 2 Y[7:0] data output in BT.1120 /
HD BT.1120 cascade input port data
HD playback port 2 C[7:0] data output in BT.1120 /
HD BT.1120 cascade input port data
HD playback BT.1120 port 2 clock output /
HD BT.1120 cascade input port clock
HD BT.1120 port 2 Y[7:0] data input
HD BT.1120 port 2 C[7:0] data input
HD BT.1120 port 2 clock input
SD BT.656 port 1 data input /
HD BT.1120 port 1 data input bit C[7:0]
SD/HD video clock input port 1 for BT.656/BT.1120
SD BT.656 port 2 data input /
HD BT.1120 port 1 data input bit Y[7:0]
SD BT.656 port 2 clock input
12

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