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PDF TW5864B1 Data sheet ( Hoja de datos )
| Número de pieza | TW5864B1 | |
| Descripción | 5D1 H264 Encoder | |
| Fabricantes | Intersil | |
| Logotipo |  |
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5D1 H264 Encoder with 4-Channel A/V Decoder &
12 Channels External VD Inputs for Security
Applications
TW5864B1
TW5864 is a H.264 encoder solution with
integrated 4-channel analog A/V decoders.
TW5864 can be used as a low cost single chip
solution for 4-channel H.264 hardware
compression PC cards, or 16-channel cards by
using additional external TW2866 chips. There are
3 versions of TW5864 that can support no
external video decoder (TW5864A), 4 channel
external video decoders (TW5864B), and 12
channel external video decoders (TW5864C).
TW5864 can also be used in embedded DVR
applications as an AV front-end chip with H264
encoding capability. It can work with existing
H.264 hardcore or DSP based CODECs. In existing
H264 CODECs, performance may be limited due
to limitation in both memory bandwidth and
hardware resources. With the H.264 encoder built
in at the front-end, the number of encoding
channel supported scales with number of
TW5864 chips used. The front-end H264 encoder
offloads the processing from the backend CODECs
to allow higher port count support and allows DSP
resources saved and reserved for product
differentiation features such as video analytic
intelligence.
support a total of 16 video input channels. The
video streams from both on-chip/off-chip video
decoders are fed into H.264 encoder as well as to
external interfaces for preview purpose. The
preview stream can go through either though four
BT. 656 video output interfaces or PCI interfaces.
The four BT 656 ports support both multi-channel
byte or line interleaved output to interface with
various external display solutions.
TW5864 has built-in de-interlacers and OSDs
before encoding is performed. There are also 16
sets of motion detection / night detection / blind
detection engine for channel alarm notification. In
addition, the hardware encoder generated motion
information of each channel is accessible to the
external CPU for analytic purpose. TW5864 also
integrates many sets of scalers for each of the
H264 encoder, MJPEG, and preview paths. Each of
these scalers is independently configured.
TW5864 provides both asynchronous host
interface and PCI interface for external CPU
control and bitstream upload. The PCI interface
can run at 33 or 66 MHz.
TW5864 features H.264 baseline level 3
compliant encoder capable of performing up to 5
D1 equivalent video encoding (125 fps for PAL
and 150 fps for NTSC), 17 channel G.726 ADPCM
hardware audio encoder with one channel for two
way audio communication. The H.264 video
encoder supports dual-bitstream compression for
both local storage and network port outputs. It
also features a motion JPEG encoder for up to 25
frames per second shared among all video
channels.
TW5864 integrates 4 A/V decoders. It has 4 CVBS
analog inputs fed into four internal high quality
NTSC/PAL video decoders. In addition, it has 3
digital BT. 656 input, running up to 108 MHz,
capable of receiving up to 12 D1 video channels
from external multi-channel video decoders such
as TW2866 / TW2867. This allows the TW5864 to
Analog Video Decoder
4 CVBS analog inputs fed into 4 sets of video
decoder accept all NTSC(M/N/4.43) / PAL
(B/D/G/H/I/K/L/M/N/60) standards with auto
detection
Integrated video analog anti-aliasing filters and
10 bit CMOS ADCs for each video decoder
High performance adaptive 4H comb filters for
all NTSC/PAL standards
IF compensation filter for improvement of color
demodulation
Color Transient Improvement (CTI)
Automatic white peak control
Programmable hue, saturation, contrast,
brightness and sharpness
Proprietary fast video locking system for non-
real-time application
Noise Reduction to remove impulse noise
1
FN7961.1
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2011, 2012. All Rights Reserved
January 10, 2012
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
TW5864B1
Table List
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Video Input Formats Supported by the TW5864........................................................................18
ITU-R BT.656 SAV and EAV Code Sequence ..............................................................................25
Special format of ITU-R BT. 656 Embedded timing code and Channel ID code when video is active27
Special format of ITU-R BT. 656 Embedded timing code and Channel ID code when video is not active
.............................................................................................................................................27
Mux Modes supported in the preview output ports ....................................................................38
Single Channel Standard ITU-R BT.656 SAV and EAV Code Sequence.........................................39
The Channel ID Format for 4 Ch Half D1 Time-multiplexed Format with 54MHz..........................41
Shows the Special format of ITU-R BT. 656 Embedded timing code and Channel ID code ............42
Line Interleaving modes supported in the first two preview output ports .....................................43
Line Interleaved modes header bytes.......................................................................................43
Line Interleaved header bytes parameters definition.................................................................44
Line Interleaved modes header bytes for Dummy Lines.............................................................44
TW5864 NAL Unit syntax.........................................................................................................47
TW5864 SPS RBSP syntax......................................................................................................47
TW5864 PPS RBSP syntax......................................................................................................48
Sequence of Multi-channel Audio Record .................................................................................53
Audio frequency 256xfs mode: AIN5MD = 0, AFS384 = 0..........................................................59
Audio frequency 320xfs mode: AIN5MD = 1, AFS384 = 0, 44.1/48 KHz not supported ..............59
Audio frequency 384xfs mode: AIN5MD = 0, AFS384 = 1, 44.1/48 KHz not supported ..............60
Audio frequency Auto Setup.....................................................................................................60
Characteristics .....................................................................................................................191
DDR Interface AC Characteristics ...........................................................................................194
DDR Interface AC Timing .......................................................................................................194
PCI Interface AC Timing .........................................................................................................197
Video Interface AC Timing......................................................................................................198
I2C Interface AC Timing .........................................................................................................199
5
5 Page 
PCI Interface
TW5864B1
NAME
PIN#
TYPE
DESCRIPTION
PCI_AD[31:0]
AD14, AE14, AF14,
AC15, AD15, AE15,
AF15, AD16, AD17,
AE17, AF17, AC18,
AD18, AE18, AF18,
AE19, AE22, AF22,
AD23, AE23, AF23,
AC24, AD24, AE24,
AC25, AD25, AE25,
AF25, AC26, AD26,
AE26, AF26
I/O PCI Address / Data Multiplexed Signals
PCI_CBE_N[3:0]
AE16, AF19, AD22,
AF24
I/O PCI Bus Command and Byte Enable Signals
PCI_PAR
AF21
I/O PCI Parity Signal
PCI_SERR_N
AE21
I/O PCI System Error Signal
PCI_PERR_N
AD21
I/O PCI Parity Error Signal
PCI_STOP_N
AC21
I/O PCI Stop Signal
PCI_DEVSEL_N
AF20
I/O PCI Device Select Signal
PCI_TRDY_N
AE20
I/O PCI Target Ready Signal
PCI_IRDY_N
AD20
I/O PCI Initiator Ready Signal
PCI_FRAME_N
AC20
I/O PCI Cycle Frame Signal
PCI_IDSEL
AC17
I/O PCI Initialization Device Select Signal
PCI_CLK
AF16
I PCI Clock Signal
PCI_REQ_N
AC14
O PCI Request Signal
PCI_GNT_N
AF13
I/O PCI Grant Signal
PCI_INTA_N
AE13
O PCI Interrupt A signal
PCI_RST_N
AB24
I PCI Reset signal
11
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