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PDF MB85RS2MT Data sheet ( Hoja de datos )
| Número de pieza | MB85RS2MT | |
| Descripción | 2M (256K x 8) Bit SPI | |
| Fabricantes | Fujitsu | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
Memory FRAM
DS501-00023-0v01-E
2 M (256 K × 8) Bit SPI
MB85RS2MT
■ DESCRIPTION
MB85RS2MT is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 262,144
words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
MB85RS2MT adopts the Serial Peripheral Interface (SPI).
The MB85RS2MT is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RS2MT can be used for 1013 read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E2PROM.
MB85RS2MT does not take long time to write data like Flash memories or E2PROM, and MB85RS2MT takes
no wait time.
■ FEATURES
• Bit configuration
: 262,144 words × 8 bits
• Serial Peripheral Interface
: SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
• Operating frequency
: 25 MHz (Max)
For FSTRD command 2.7 V to 3.6 V, 40 MHz (Max)
• High endurance
: 1013 times / byte
• Data retention
: 10 years (+85 °C)
• Operating power supply voltage : 1.8 V to 3.6 V
• Low power consumption
: Operating power supply current 10.6 mA (Max@25 MHz) (TBD)
Standby current 150 μA (Max) (TBD)
Sleep current 10 μA (Max) (TBD)
• Operation ambient temperature range : -40 °C to +85 °C
• Package
: 8-pin plastic SOP (FPT-8P-M08)
8-pin plastic DIP (DIP-8P-M03)
RoHS compliant
Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.3
1 page  
MB85RS2MT
■ SERIAL PERIPHERAL INTERFACE (SPI)
MB85RS2MT works as a slave of SPI. More than 2 devices can be connected by using microcontroller
equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus
connected to use.
SCK
MOSI
MISO
SPI
Microcontroller
SO SI SCK
MB85RS2MT
SO SI SCK
MB85RS2MT
CS HOLD CS HOLD
SS1
SS2
HOLD1
HOLD2
System Configuration with SPI Port
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select
Microcontroller
SO SI SCK
MB85RS2MT
CS HOLD
System Configuration without SPI Port
DS501-00023-0v01-E
5
5 Page 
MB85RS2MT
• SLEEP
The SLEEP command shifts the LSI to a low power mode called “SLEEP mode”. The transition to the SLEEP
mode is carried out at the rising edge of CS after operation code in the SLEEP command. However, when
at least one SCK clock is inputted before the rising edge of CS after operation code in the SLEEP command,
this SLEEP command is canceled.
After the SLEEP mode transition, SCK and SI inputs are ignored and SO changes to a Hi-Z state.
CS
SCK
Enter Sleep Mode
01234567
SI Invalid 1 0 1 1 1 0 0 1 Invalid
SO Hi-Z
Sleep Mode Entry
Returning to an normal operation from the SLEEP mode is carried out after tREC (Max 400 μs) time from the
falling edge of CS (see the figure below). It is possible to return CS to H level before tREC time. However, it
is prohibited to bring down CS to L level again during tREC period.
CS
CS
tREC From this time
Command input enable
Exit Sleep Mode
Sleep Mode Exit
DS501-00023-0v01-E
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet MB85RS2MT.PDF ] | |
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